Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-10-30
2003-06-10
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C327S403000
Reexamination Certificate
active
06577263
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is related to an analog switch, and a sample-and-hold circuit for an analog input voltage. More specifically, the present invention is directed to such a technique capable of reducing an adverse influence caused by such a voltage which has already been inputted into an analog multiplexer. For instance, the present invention is pertinent to such an effective technique which is utilized in an A/D converting circuit, and also a single-chip microprocessor computer having the A/D converting circuit therein.
In an A/D (analog-to-digital) converting circuit, and a semiconductor integrated circuit containing this A/D converting circuit, an analog switch, and a sample-and-hold circuit are employed. The analog switch is used so as to conduct an analog input voltage from an external source, and this analog input voltage should be A/D-converted. The sample-and-hold circuit holds the analog input voltage while being A/D-converted. Also, in the case that there are plural analog signals derived from a plurality of sensors as realized in a control system for an automobile, when each of these plural analog signals is A/D-converted into a digital signal by using a respective one of the individual A/D converting circuits, a total number of these A/D converting circuits becomes large, so that cost of the automobile control system would be increased. As a consequence, such an automobile control system may be sometimes arranged in such a manner that a plurality of analog input voltages are A/D-converted in a time divisional manner by employing a single A/D converting circuit.
FIG. 20
represents such a time-divisional type A/D converting system. This system is arranged as follows: That is, in this A/D converting system, a plurality of analog input voltages Vin
1
, Vin
2
, ---, Vinn are selected by a multiplexer MPX one by one, and then, the selected analog input voltages are acquired by a sample-and-hold circuit SH. Thus, a plurality of analog input voltages are A/D-converted in the time divisional manner by using a single A/D converting circuit ADC.
SUMMARY OF THE INVENTION
In the A/D converting system as indicated in
FIG. 20
, analog switches SWc
1
to SWcn which constitute the multiplexer MPX, and a sampling switch SWs of the sample-and-hold circuit SH are constituted by employing MOSFETs. On the other hand, in the A/D converting system of
FIG. 20
, a stray capacitance Ca is produced at a connection node NO between the analog switches SWc
1
to SWcn of the respective channels which constitute the multiplexer MPX, and the sampling switch SWs which constitutes the sample-and-hold circuit SH.
The production of the above-described stray capacitance Ca is caused by a junction capacitance and a wiring capacitance between a source (drain) and a main body (well) of an MOSFET. When the Inventors of the present invention tried to calculate such a stray capacitance of a circuit having 8 channels, this stray capacitance was approximately 30 pF (picofarad). Also, another stray capacitance Ca is produced at an input terminal of an A/D converting circuit
30
of FIG.
20
. Furthermore, as a capacitance value of a sampling capacitor Cs which constitutes this sample-and-hold circuit SH, such sampling capacitors having capacitance values of, for example, approximately 5 to 6 pF are used.
On the other hand, in order to improve the response characteristic of the sample-and-hold circuit SH, impedances (ON-resistances) of the analog switches SWc
1
to SWcn, and also an impedance (ON-resistance) of the sampling switch SWs are preferably made low. For instance, in the case that sampling time is selected to be on the order of 3 &mgr;s (microseconds), an impedance of such a sample-and-hold circuit may be preferably selected to be lower than, or equal to 1 k&OHgr; (killoohms).
However, the following risk problem can be revealed. That is, when the channels are switched by the multiplexer MPX, if the impedances of the analog switches SWc
1
to SWcn are low and further the stray capacitance Ca is produced at the connection node NO between the analog switches SWc
1
to SWcn and the sampling switch SWs, the electron charge which has been stored in this stray capacitance Ca before the channels are switched may give an adverse influence to a level of a next analog input voltage which is inputted via such an analog switch which is turned ON after the channels are switched by the multiplexer MPX. As a result, an error of the analog input voltage to be sampled would be increased.
To avoid this problem, in such a control system as shown in
FIG. 20
in which while the channels are switched by the multiplexer MPX, the A/D converting operation is carried out in the time divisional manner, it is preferable to connect externally-connectable capacitors Ci
1
to Cin each having capacitances of approximately 0.1 &mgr;F to the respective analog input terminals AIN
1
to AINn. The reason why the error can be reduced is given as follows. That is, when such externally-connectable capacitances Ci
1
to Cin are connected to these analog input terminals AIN
1
to AINn, electron charges are redistributed via such an analog switch which is turned ON between the stray capacitance Ca and any one of these externally-connectable capacitors Ci
1
to Cin, which may reduce the error of the analog input voltage to be sampled.
FIG. 21
graphically shows a relationship between an internal impedance Rin of an analog signal source and an error &dgr; (LSB) of an analog input voltage Vin to be sampled, assuming now that the capacitance values of the externally-connectable capacitors Ci
1
to Cin which are connected to the analog input terminals AIN
1
to AINn are constant. In this case, it is so assumed that the error &dgr; (LSB) may be expressed by the following formula (1) under such a condition that resolution of the A/D converting circuit is selected to be 10 bits, a reference voltage is selected to be Vref, and also a voltage which is actually acquired into the sampling capacitor Cs is selected to be “Vs”:
&dgr;(
LSB
)=(
V
in−
Vs
)/(
V
ref/1024) (1)
In this drawing of
FIG. 21
, a solid line “a” indicates such an error plotted in the case that the capacitance value of the externally-connectable capacitor Ci is equal to 0.1 &mgr;F. A broken line “b” indicates such an error plotted in the case that the capacitance value of the externally-connectable capacitor Ci is equal to 0.07 &mgr;F. Also, a dotted line “c” indicates such an error plotted in the case that the capacitance value of the externally-connectable capacitor Ci is equal to 0.05 &mgr;F.
It should be noted that the relationship of
FIG. 21
is obtained under the below-mentioned condition: That is, a range of an operation voltage is selected to be zero V to +0.5 V and −0.5 V; sampling time of an analog input voltage is selected to be 3.2 &mgr;S; an equivalent capacitance value (Ca+Cs+Cd) defined from an analog input terminal AIN up to a sample-and-hold circuit is selected to be approximately 50 pF; and further, both an equivalent impedance of an analog switch SWc of a multiplexer and another equivalent impedance of a sampling switch SWs own such a characteristic represented in FIG.
22
. In
FIG. 22
, a curve indicated as a symbol “WORST” denotes an impedance of such an element having the largest fluctuation. Also, a curve indicated as a symbol “TYP” denotes an impedance of a typical element.
The following fact can be seen from FIG.
21
. That is, the larger the capacitance values of the externally-connectable capacitors Ci
1
to Cin of the analog input terminals AIN
1
to AINn become, the smaller the error is decreased. However, when the capacitance values of the externally-connectable capacitors Ci
1
to Cin are increased in an automobile control system, the following fact could be revealed. That is, there is a certain possibility that precision of the A/D converting operation is lowered. Under such a circumstance, the Inventors of the present invention has considered this reason of lowering of the A/D
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