Method for minimizing stress between semiconductor chips having

Details Method for minimizing stress between semiconductor chips having Method for minimizing stress between semiconductor chips having

1992-11-12

1993-12-21

Kunemund, Robert

Fishing, trapping, and vermin destroying

437248, 156 80, H01L 2158, H01L 2184

Patent

active

052721132

ABSTRACT:
Semiconductor chips, such as photosensor arrays in a full-width scanner, are mounted on a substrate to maintain reasonably consistent spacing among chips regardless of temperature conditions during use. After chips are tacked onto the substrate with uncured epoxy, the assembly is brought to a low temperature prior to the heating of the curing step. The technique permits design of the assembly to compensate for differences between the thermal coefficient of expansion of the chips and that of the substrate, while also minimizing mechanical stresses on the chips caused by heating in the course of use.

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"Laminating Technique for Copper Inner Planes of Multilayer Printed Circuit Board"; IBM Technical Disclosure Bulletin, vol. 25, No. 11B Apr. 1983 T. J. Carey, Jr. et al.

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