Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-12-07
2003-06-24
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C336S200000
Reexamination Certificate
active
06582989
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to photolithographically-patterned, out-of-plane coil structures for use in integrated circuits, circuit boards and other devices.
2. Description of Related Art
Standard bonding techniques for electrically connecting integrated circuits, or chips, to a circuit board or other device include wire bonding, tab bonding, and solder-bump flip-chip bonding.
FIG. 1
shows a contact pad
3
formed on a chip
2
wire bonded to a corresponding contact pad
3
formed on a substrate
1
. The contact pads
3
are electrically connected, or bonded, by a wire
4
. Since the chip
2
typically has tens or even hundreds of the contact pads
3
, wire bonding each contact pad
3
on the chip
2
to the corresponding contact pad
3
on the substrate
1
is labor intensive, expensive and slow. Further, the contact pads
3
must be large enough to accommodate both the wire
4
and the accuracy of the wire bonding device used to create the wire bond. Therefore, the contact pads
3
are made larger than otherwise necessary to compensate for the size limitations of wire
4
and the wire bonding device.
FIG. 2
shows the contact pad
3
formed on the chip
2
tab bonded to the corresponding contact pad
3
on the substrate
1
. A flexible substrate
5
having conductive lines formed on its lower surface is forced against the contact pads
3
. A layer of anisotropic adhesive (not shown) is placed between the contact pads
3
and the flexible substrate
5
. When the flexible substrate
5
is pressed against the contact pads
3
, the anisotropic adhesive and the conductive lines formed on the flexible substrate
5
cooperate to complete the electrical connection between the contact pads
3
. Like wire bonding, tab bonding suffers from yield loss and high cost. Irregularities in the heights of the contact pad
3
result in non-uniform contacting force pressing the flexible substrate
5
against the contact pads
3
. The non-uniform contacting force means that some contact pads
3
will not be properly bonded to the flexible substrate
5
.
Another conventional method for bonding the contact pads
3
formed on the chip
2
to the contact pads
3
formed on the substrate
1
or to some other device is solder-bump flip-chip bonding.
FIG. 3
shows the chip
2
inverted with the contact pads
3
facing toward the substrate
1
. The name “flip-chip” derives from the inversion of the chip
2
, since the chip
2
is “flipped over” with the contacts pads
3
facing the substrate
1
, in contrast to both tab bonding and wire bonding where the contact pads
3
on the chip
2
face away from the substrate
1
. In standard flip-chip bonding, solder bumps
6
are formed on the contact pads
3
on the substrate
1
. The electrical connection between the corresponding contact pads
3
is completed by pressing the contact pads
3
on the chip
2
against the solder bumps
6
.
Flip-chip bonding is an improvement over both wire bonding and tab bonding. The relatively soft solder bumps
6
tend to permanently deform when the chip
2
is pressed down against the solder bumps
6
. This deformation of the solder bumps
6
compensates for some irregularity in the heights of the contact pads
3
and any uneven contacting pressure forcing the chip
2
against the solder bumps
6
.
However, flip-chip bonding does suffer from both mechanical and thermal variations in the solder bumps
6
. If the solder bumps
6
are not uniform in height or if the substrate
1
is warped, contact between the contact pads
3
and the solder bumps
6
can be broken. Also, if the contacting pressure forcing the chip
2
down on the solder bumps
6
is uneven, contact between some contact pads
3
and corresponding solder bumps
6
can fail.
FIG. 4
shows a standard technique for establishing a temporary electrical contact between two devices. A probe card
7
having a plurality of probe needles
8
contacts the contact pads
3
by physically pressing the probe needles
8
against the contact pads
3
. The physical contact between the probe needles
8
and the contact pads
3
creates an electrical connection between the probe needles
8
and the lines
9
formed on the substrate
1
.
The probe cards
7
are generally used to create only temporary contacts between the probe needles
8
and the contact pads
3
, so that the device
10
can be tested, interrogated or otherwise communicated with. The device
10
can be a matrix of display electrodes which are part of an active-matrix liquid crystal display. Testing of the devices
10
, such as liquid crystal display electrode matrices, is more thoroughly described in an application JAO 34053 to the same inventor, co-filed and co-pending herewith and herein incorporated by reference.
The probe cards
7
have many more applications than only for testing liquid crystal displays. Any device
10
having numerous and relatively small contact pads
3
, similar to those found on the chip
2
, can be tested using the probe card
7
. However, standard techniques for producing the probe card
7
are time consuming and labor-intensive. Each probe card
7
must be custom-made for the particular device
10
to be tested. Typically, the probe needles
8
are manually formed on the probe card
7
. Because the probe cards
7
are custom-made and relatively expensive, the probe cards
7
are not typically made to contact all of the contact pads
3
on the device
10
at one time. Therefore, only portions of the device can be communicated with, tested or interrogated at any one time, requiring the probe card
7
be moved to allow communication, testing or interrogation of the entire device
10
.
The probe cards
7
are also used to test the chips
2
while the chips
2
are still part of a single-crystal silicon wafer. One such probe card
7
is formed by photolithographic pattern plated processing, as disclosed in Probing at Die Level, Corwith, Advanced Packaging, February, 1995, pp. 26-28. Photolithographic pattern plated processing produces probe cards
7
which have essentially the same design as the standard probe card
7
. However, this new type of processing appears to automate the method for producing probe needles
8
, thus avoiding manually forming the probe needles
8
. Also, this article discloses a probe card
7
which is bent at the end nearest the probe needles
8
, as shown in FIG.
5
. The bend in the probe card
7
allows the probe needles
8
to contact the contact pad
3
at an angle. As the probe card
7
pushes the probe needles
8
into the contact pads
3
, a mechanical scrubbing action occurs which allows the probe needles
8
to break through the oxide formed on the top surface of the contact pad
3
.
All of the standard probe cards
7
, however, are limited to testing contact pads
3
which are arranged in a linear array. Also, the standard probe cards
7
are sensitive to variations in the height of the contact pads
3
on the substrate
1
, irregularities or warping of the substrate
1
, and temperature variations.
The integration of small inductors on silicon substrates has been the subject of intense worldwide research for more than 15 years. This effort is driven by the desire to integrate coils on silicon and gallium arsenide integrated circuits (ICs). The structures proposed so far, however, have been variations of devices in which, due to technological constraints, the coil windings have almost always been implemented as spirals parallel to the underlying substrate.
These in-plane architectures have two major drawbacks. When made on a substrate that is slightly conducting such as silicon, the coil magnetic fields induce eddy currents in the underlying substrate. These currents cause resistive dissipation that contributes to the coil losses. The second problem arises when the coil is operated at high frequencies, where skin and proximity effects force the coil current to flow along the outer surfaces of the conductor. The “skin depth” is about 2 to 3 &mgr;m for typical conductors at frequencies of interest
Biegelsen David K.
Chua Christopher L.
Fork David K.
Dang Phuc T.
Nelms David
Walder Jeannette M.
Xerox Corporation
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