Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2002-02-06
2003-07-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
63
Reexamination Certificate
active
06589816
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electronic and semiconductor devices, and more particularly, to a method of forming electrical connections in integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits are formed on circular wafers of semiconductor material, which is typically monocrystalline silicon. Each wafer contains a large number of dies of the same device which, upon completion of the processing of the wafer, are separated to be mounted on suitable support structures and to be electrically connected to metal pins for connection to external circuits.
The final stages of the processing of the wafer includes the formation of a layer of dielectric material on the semiconductor substrate, and the formation of electrical connections between components of each integrated circuit. That is, the electrical connections are conductive elements for electrically connecting areas of the semiconductor substrate to other areas of the same substrate, or to areas of conductive layers formed thereon.
A known technique for forming electrical connection elements uses the deposition of a metal by electrochemical means. To initiate deposition of this type, it is necessary to deposit a conductive base layer (a seed layer) which enables an electrical connection to be established between the areas to be metallized and the negative electrode of the voltage supply used for the treatment. The seed layer must have low resistivity and a controlled thickness to ensure uniform current throughout the wafer during the electrochemical treatment, and must also adhere well to the dielectric layer which is normally an oxide and covers the wafer. The seed layer must also be compatible with the metal to be deposited.
Metals or alloys of metals which are no less noble than the metal to be used for the electrochemical deposition, that is, which do not react spontaneously with the electrolyte of the electrolytic bath, are used as the seed layer. Copper is often used for the seed layer, particularly if copper is also to be used for the connection elements. However, copper, like other metals that may be used for the seed layer, does not have good adhesion to the oxide and tends to diffuse into it. As is known, before the seed layer is formed, an intermediate layer of a metal which has a strong attraction for oxygen atoms and which at the same time ensures a good inter-metallic bond with the seed layer is therefore formed. The intermediate layer, also known as the barrier layer, also serves to prevent or at least reduce the diffusion of the metal of the seed layer into the underlying oxide layer.
A refractory metal or an alloy thereof, for example, Ta, TaNx, Cr, CrNx, Ti, TiNx, W, and WNx is deposited by sputtering or by chemical vapor deposition (CVD). This metal is usually selected for the barrier layer. As stated above, copper, which is deposited by sputtering or by electroless plating, is often selected for the seed layer.
The thickness necessary for the seed layer is determined on the basis of the dimensions of the wafer. For electrochemical treatment, the wafer, or more precisely, the seed layer which covers it, extends to the edges. The larger the wafer, the thicker the seed layer must therefore be to ensure good uniformity of the layer deposited, even in the central regions of the wafer.
With the tendency to use wafers of ever larger diameters, the need for a thicker seed layer is greater. However, a large thickness of the seed layer leads to problems since the removal of the seed layer after it has performed its function also entails the removal of metal from the connection elements which have just been formed. This reduces the width and thickness of the connection elements.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of the present invention is to provide a method of forming metal connection elements which uses electrochemical deposition, which does not require very thick seed layers, and which ensures optimal uniformity of thickness of the connection elements.
These and other objects, advantages and features according to the present invention are provided by a method for forming metal connection elements in a plurality of integrated circuits on a wafer. The method comprises forming a seed layer on the wafer, and forming a first mask on the seed layer covering the plurality of integrated circuits while exposing first portions of the seed layer overlying scribe lines used for separating the integrated circuits. Conductive strips are formed on the first portions of the seed layer.
The method further comprises removing the first mask, and forming a second mask on the conductive strips while exposing second portions of the seed layer. Metal connection elements are formed on the second portions of the seed layer by electrochemical deposition using the seed layer as a cathode.
REFERENCES:
patent: 2002/0130394 (2002-09-01), Toyoda
patent: 0928016 (1999-07-01), None
Patent Abstracts of Japan, vol. 015, No. 454 (E-1137), Nov. 25, 1991 & JP 03198342 A (Nec Corp.), Aug. 29, 1991.
Patent Abstracts of Japan, vol. 017, No. 028 (E-1308), Jan. 19, 1993 & JP 04250628 A (Nippon Steel Corp.), Sep. 7, 1992.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Le D
Nelms David
STMicroelectronics S.r.l.
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