Low power architecture for register files

Details Low power architecture for register files Low power architecture for register files

2001-06-28

2003-07-22

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S194000, C365S227000

Reexamination Certificate

active

06597623

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to register files, and more particularly, to a low power architecture for register files.
BACKGROUND
A small, high-speed computer circuit that holds values of internal operations, such as the address of the instruction being executed and the data being processed is termed as a register. For example, when a program is debugged, register contents may be analyzed to determine the computer's status at the time of failure. In microcomputer assembly language programming, programmers reference registers routinely.
Large register files are an important component of today's high-speed microprocessors. For performance reasons, the register file uses dynamic logic and hence significant power dissipation occurs due to the required clocking. What is needed is an architecture that eliminates the need for high-activity clock signals, thereby resulting in lower power dissipation.


REFERENCES:
patent: 5233565 (1993-08-01), Wang
patent: 5357479 (1994-10-01), Matsui
patent: 6044035 (2000-03-01), Kohno
patent: 6195308 (2001-02-01), Durham et al.

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