SOI voltage-tolerant body-coupled pass transistor

Details SOI voltage-tolerant body-coupled pass transistor SOI voltage-tolerant body-coupled pass transistor

1999-09-17

2003-09-30

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S537000

Reexamination Certificate

active

06628159

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to transistor devices which have a dynamic threshold and more particularly to a dynamic threshold device which has increased current capabilities.
2. Description of the Related Art
Silicon-On-Insulator (SOI) technology, which is becoming of increasing importance in the field of integrated circuits, deals with the formation of transistors in a relatively thin layer of semiconductor material overlying a layer of insulating material. Devices formed on SOI offer many advantages over their bulk counterparts, including: higher performance, absence of latch-up, higher packing density, low voltage applications, etc. However, SOI circuits, like other electronic circuits, are: First, susceptible to electrostatic discharge (ESD), a surge in voltage (negative or positive) that occurs when a large amount of current is applied to the circuit; and second, in need of providing an ideality (a constant voltage swing of 60 mV/decade over several decades of current) for analog applications, such as in phase-locked-loop circuits, voltage regulators, and band gap reference circuits.
For ESD applications, to discharge ESD impulses, ESD protection schemes need a low voltage turn-on and a high current drive (the ability to generate or sink a large amount of current before a large amount of negative or positive voltage is developed). Traditional bulk overvoltage protection schemes, such as diode circuits, do not work well on SOI because of the presence of the SOI buried oxide. That is, conventional diodes on SOI have small current drivability because the current is carried laterally and is limited by the thickness of the semiconductor material. Thus, developing a new approach or a new type of diode was necessary for adequate ESD protection for SOI circuits.
ESD robustness is important for SOI driver (buffer) and receiver circuits. Receiver circuits, pass transistors, test transistors, feedback keeper elements and other auxiliary transistors on input pins must be overvoltage tolerant to protect from ESD events, electrical overstress, and other high current and voltage conditions. Hence, robust elements are needed to provide ESD robust SOI receiver circuits. Input/output (I/O) networks and off-chip drivers must also provide ESD robust pull-up and pull down elements. Hence, n-channel or p-channel SOI transistors, used as both pull-up or pull-down elements must provide over-shoot and undershoot protection, electrical overstress protection and ESD protection.
An I/O circuit is very susceptible to gate overstress, overvoltage and electrostatic discharge/electrical overstress events. The pass transistor, typically used in receiver networks, bi-directional circuits and other applications is extremely useful in protecting against overvoltage and electrostatic discharge events.
For overvoltage events, there are both positive and negative overshoot concerns that are typically addressed for receiver networks. For ESD events, there are both positive and negative events that occur on both the source and drain of the pass transistor (input or output side). Human body model (HBM) and machine model (MM) events occur on the pad side of the structure. Charged device model (CDM) events can occur on the receiver side. In all cases, voltage across the pass transistor that allows it to undergo secondary breakdown is a concern. In SOI technologies, there is also a concern that the diode is not formed relative to the bulk substrate. This prevents the operation of diode action relative to the bulk for negative undershoot or negative mode ESD phenomenon.
SUMMARY OF THE INVENTION
In one aspect, the invention provides a structure, method and apparatus which uses a body-limiting network in an ESD device on SOI chips. The invention uses a body-charging network to produce a more robust ESD. The invention uses an SOI body-augmenting network which modulates an SOI body potential and provides a more robust ESD network. The invention provides RC discrimination and a body-limiting network in an ESD network on an SOI chip. The invention also provides RC discrimination and body-charging networks in an ESD network.
The invention includes RC discrimination and a SOI-body augmented network in an ESD network. The invention provides a RC discrimination-body controller, a body-modulation network, a SOI body-augmenting network, and a body-charging network, all for a half-pass transistor.
Thus, the invention provides a structure and method for a pass transistor device which includes a source, a drain opposite the source, a body between the source and the drain, and a circuit control network connected between the drain and the source (the circuit control network controls a potential voltage of the body and provides overvoltage protection to the pass transistor). The circuit control network includes a body-charging element. The body-charging element includes a Lubistor, a body- and gate-coupled silicon over insulator (SOI) diode element, at least one Lubistor, a silicon over insulator (SOI) metal oxide silicon field effect transistor (MOSFET), and a body- and gate-coupled silicon over insulator (SOI) metal oxide silicon field effect transistor (MOSFET) diode. The circuit control network includes a body-limiting element and a voltage divider network. The voltage divider includes at least one resistor. The resistor includes a buried resistor element and a silicon over insulator (SOI) metal oxide silicon field effect transistor (MOSFET). The circuit control network includes at least one resistor-capacitor series configured element whose center node is connected to the SOI body of the pass transistor.
Another embodiment of the invention is a silicon over insulator (SOI) metal oxide silicon field effect transistor (MOSFET) device which includes a body, a gate opposite the body, a resistive/capacitor discriminator connected to the gate, and a circuit control network connected to the body (wherein a potential voltage of the body is modulated by the control circuit network to provide electrostatic discharge (ESD) protection). The control circuit is connected to the gate, modulates the potential voltage of the body, and limits the body to a reference voltage. The control circuit includes at least one SOI MOSFET, at least one ESD SOI diode, at least one body/gate-coupled SOI diode, and n-channel and p-channel SOI MOSFETs, at least two RC discriminators and at least one control circuit network. The device further includes an input pad connected to the gate, a drain adjacent the gate, and a source opposite the drain (wherein the control network is connected to the input pad and the drain and the source is connected to Vss).


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