Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2001-08-15
2003-03-18
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S243000, C438S244000, C438S387000
Reexamination Certificate
active
06534376
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the fabrication of integrated circuits (IC's), and more particularly to the fabrication of memory IC's.
BACKGROUND
Semiconductor devices are used in a variety of electronic applications, such as personal computers and cellular phones, for example. One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and one common type of semiconductor memory is a dynamic random access memory (DRAM).
A DRAM typically includes millions or billions of individual DRAM cells arranged in an array, with each cell storing one bit of data. A DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
DRAM storage capacitors are typically formed by etching deep trenches in a semiconductor substrate, and depositing a plurality of layers of conductive and insulating materials in order to produce a storage capacitor that is adapted to store data, represented by a one or zero. Prior art DRAM designs typically comprise an access FET disposed in a subsequently deposited layer, disposed above and to the side of the storage capacitor.
The semiconductor industry in general is being driven to decrease the size of semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today's semiconductor products. More recent DRAM designs involve disposing the access FET directly above the storage capacitor, sometimes referred to as a vertical DRAM, which saves space and results in the ability to place more DRAM cells on a single chip.
An element known as a sacrificial collar is a sacrificial component that is temporarily disposed on the upper portion of storage cell deep trenches during the manufacturing of a DRAM. A sacrificial collar is used to protect the trench sidewall in the top area of the trench. This area houses the vertical FET and the buried strap region that couples the storage cell to the access FET in the finished DRAM device. The area extends from the surface to the highly doped area called buried plate.
While a sacrificial collar is in place, various process steps are performed on the bottom part of a deep trench, such as the widening of the deep trench below the sacrificial collar, which is often referred to as bottle etch, and various doping of the substrate within the deep trench. A sacrificial collar is typically replaced by more permanent insulating collars later in the manufacturing process.
SUMMARY OF THE INVENTION
Embodiments of the present invention achieve technical advantages as a sacrificial collar with a vertical thermal nitride mask having a greater thickness than prior art sacrificial collars with a vertical thermal nitride mask. The nitride liner layer that forms the sacrificial collar is deposited in a deposition step such as a chemical-vapor deposition (CVD) process, so that the thickness of the sacrificial collar deposited is well-controlled and may be achieved to the desired thickness.
In one embodiment, disclosed is a method of processing a semiconductor device that includes a deep trench formed within a substrate, the method comprising depositing a nitride liner layer over the deep trench, depositing a semiconductor layer over the nitride liner layer, and forming a first oxide layer over a lower portion of the semiconductor layer so that an upper portion of the semiconductor layer is exposed. The method includes forming a nitride layer over the exposed upper portion of the semiconductor layer, removing the first oxide layer, leaving the lower portion of the semiconductor layer exposed, removing the exposed semiconductor layer, leaving a lower portion of the nitride liner layer exposed, and removing the exposed nitride liner layer lower portion and the nitride layer from the upper portion.
Also disclosed is a method of manufacturing a semiconductor memory cell, comprising providing a semiconductor substrate, forming a trench in the substrate, and depositing a nitride liner layer over the substrate. A semiconductor layer is deposited over the nitride liner layer, a first oxide layer is formed over the semiconductor layer. In a next step, the trench is filled with resist. The resist is removed from the top portion of the trench, to leave a bottom portion of the resist within the trench, leaving a portion of the first oxide layer exposed. The exposed first oxide layer portion is removed, to leave a portion of the semiconductor layer exposed. The resist in the trench bottom portion is removed to leave a portion of the first oxide layer exposed. A nitride layer is formed over the exposed semiconductor layer portion, and the exposed first oxide layer portion is removed, leaving a lower portion of the semiconductor layer exposed. The exposed semiconductor layer lower portion is removed, leaving a lower portion of the nitride liner layer exposed. The exposed nitride liner layer lower portion and the nitride layer in the upper portion of the trench are removed.
Further disclosed is a method of processing a semiconductor device having a substrate, the method comprising forming a first layer comprised of a first material over the substrate, forming a second layer comprised of a second material over the first layer, forming a third layer comprised of a third material over a portion of the second layer so that a portion of the second layer is exposed, and forming a fourth layer comprised of the first material over the exposed portion of the second layer. The method includes removing the third layer, leaving a portion of the second layer exposed, removing the exposed second layer, leaving a portion of the first layer exposed, and removing the exposed first layer lower portion and the fourth layer.
Advantages of embodiments of the invention include the ability to control the thickness of a sacrificial collar to a greater degree than in the prior art. A wide range of sacrificial collar thicknesses may be achieved with embodiments of the present invention. A semiconductor wafer utilizing the increased thickness sacrificial collar in accordance with embodiments of the present invention may be subject to further processing, such as a plurality of cleaning steps and gas phase doping steps, without damage to or removal of the sacrificial collar. Fewer subsequent bottle etch steps may be required because portions of the substrate within trenches may be removed during the removal of semiconductor layer residing over the sacrificial collar.
REFERENCES:
patent: 6261972 (2001-07-01), Tews et al.
patent: 6309924 (2001-10-01), Divakaruni et al.
patent: 6376324 (2002-04-01), Mandelman et al.
patent: 6429092 (2002-08-01), Beintner et al.
Infineon - Technologies AG
Lytle Craig P.
Slater & Matsil L.L.P.
Smith Matthew
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