Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing
Reexamination Certificate
2000-05-01
2003-05-27
Lim, Krisna (Department: 2153)
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
C709S236000, C370S392000, C370S389000
Reexamination Certificate
active
06571291
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of The Invention
The present invention relates to layer
2
(and above) switching of data packets in a non-blocking network switch configured for switching data packets between subnetworks and more particularly to updating a layer
3
checksum as a result of modifying the corresponding layer
3
header.
2. Background Art
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access control (MAC) enabling network interface devices at each network node to access the network medium.
The Ethernet protocol IEEE 802.3 has evolved to specify a half-duplex media access mechanism and a full-duplex media access mechanism for transmission of data packets. The full-duplex media access mechanism provides a two-way, point-to-point communication link between two network elements, for example between a network node and a switched hub.
Switched local area networks are encountering increasing demands for higher speed connectivity, more flexible switching performance, and the ability to accommodate more complex network architectures. For example, commonly-assigned U.S. Pat. No. 5,953,335 discloses a network switch configured for switching layer
2
type Ethernet (IEEE 802.3) data packets between different network nodes; a received data packet may include a VLAN (virtual LAN) tagged frame according to IEEE 802.1q protocol that specifies another subnetwork (via a router) or a prescribed group of stations. Since the switching occurs at the layer
2
level, a router is typically necessary to transfer the data packet between subnetworks.
Efforts to enhance the switching performance of a network switch to include layer
3
(e.g., Internet protocol) processing may suffer serious drawbacks, as current layer
2
switches preferably are configured for operating in a non-blocking mode, where data packets can be output from the switch at the same rate that the data packets are received. Newer designs are needed to ensure that higher speed switches can provide both layer
2
and above switching capabilities for faster speed networks such as 100 Mbps or gigabit networks.
However, such design requirements risk loss of the non-blocking features of the network switch, as it becomes increasingly difficult for the switching fabric of a network switch to be able to perform layer
3
processing at the wire rates (i.e., the network data rate).
If layer
3
information is processed at a network switch, the layer
3
checksum must be validated and updated. For example, if the “time to live” field of an IP header is decremented, the IP header content has been changed and thus, the IP checksum must be updated. Conventional implementations typically would buffer the IP header portion of a frame and recalculate the sixteen bit IP checksum in an internal rules checker of a network switch port before the IP portion of a frame is transmitted. Such an implementation, however, would require substantial resources and add substantially to the latency encountered by the data packet.
SUMMARY OF THE INVENTION
There is a need for an arrangement that enables a network switch to provide layer
2
switching and layer
3
switching capabilities for 100 Mbps and gigabit links without blocking of the data packets.
There is also a need for an arrangement that provides validation and an incremental update of the IP checksum in real time without the need to buffer and recalculate the entire IP checksum before each IP frame is transmitted.
These and other needs are attained by the present invention, where a network switching system is configured for evaluating an incoming data packet including layer
3
information having an Internet Protocol (IP) header and an IP checksum. The system includes a buffer memory and network switch. The network switch includes a media access control (MAC) module having a receive data portion and a transmit data portion. The receive data portion is configured to extract the IP checksum from the IP header and to validate the IP checksum. A queue block is configured to send the IP checksum along with the received data frame to the buffer memory for storage therein. A layer
3
internal rules checker is configured to receive layer
3
information and to modify the IP header based on a field of the IP header. The internal rules checker generates an identifier indicating whether the field needs to be changed. The network switch also includes a dequeue block configured to receive the identifier and to retrieve the IP checksum from the buffer memory and to incrementally update the IP checksum as a result of the change to the field, with the updated IP checksum being received by the transmit data portion of the MAC module.
Another aspect of the invention provides a method of updating an IP checksum of a data packet at a network switching system. The method includes receiving, at a network switch, a data packet including layer
3
information having an Internet Protocol (IP) header and an IP checksum. The IP checksum is validated and stored in a buffer memory. The IP header is modified. The IP checksum is retrieved from the buffer memory and is incrementally updated to correspond to the modified IP header. The data packet is then transmitted from the network switch with the updated IP checksum.
Thus, the apparatus and method of the invention advantageously provides an incremental update of the IP checksum in real time which reduces memory requirements and the processing time associated with updating the IP checksum.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the present invention may be realized and attained by means of instrumentalities and combinations particularly pointed in the appended claims.
REFERENCES:
patent: 5953335 (1999-09-01), Erimli et al.
patent: 6128666 (2000-10-01), Muller et al.
patent: 6226680 (2001-05-01), Boucher et al.
patent: 6256314 (2001-07-01), Rodrig et al.
patent: 6345302 (2002-02-01), Bennett et al.
patent: 6389479 (2002-05-01), Boucher et al.
patent: 6434620 (2002-08-01), Boucher et al.
patent: 6449656 (2002-09-01), Elzur et al.
patent: 6496505 (2002-12-01), La Porta et al.
Mallory Et Al., “Incremental Updating of the Internet Checksum”, Request for Comments 1141, Network Working Group, Internet Engineering Task Force, Jan., 1990, pp. 1-2.
Advanced Micro Devices , Inc.
Lim Krisna
Manelli Denison & Selter PLLC
Stemberger Edward J.
Turkevich Leon R.
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