Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-07-20
2003-08-19
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S523000
Reexamination Certificate
active
06609143
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an arithmetic logic unit and arithmetic/logical operation method for realizing high-speed multiply, multiply-and-accumulate and other operations that are frequently used in signal processing.
BACKGROUND ART
In the past, multi-media data was processed using a microprocessor and a dedicated LSI in combination. However, thanks to recent amazing performance enhancement of microprocessors, it is now possible for a microprocessor to execute some types of multi-media data processing by itself. The development of a register-divided operation method was one of the factors contributing to this performance enhancement achieved. Also, in the fields of image processing, audio processing and so on, an operation method of deriving a single accumulated data word from input array elements is often used.
FIG. 12
illustrates a configuration for a known arithmetic logic unit performing a multiply-and-accumulate operation using a divided register.
In
FIG. 12
, a register
105
stores 32-bit accumulated data words ZU and ZL as its high- and low-order 32 bits, respectively. A multiplier
101
receives and multiplies together the high-order 16 bits of an input 32-bit data word X (hereinafter, referred to as “XU”) and the high-order 16 bits of another input 32-bit data word Y (hereinafter, referred to as “YU”) and outputs a 32-bit product. A multiplier
102
receives and multiplies together the low-order 16 bits of the input data word X (hereinafter, referred to as “XL”) and the low-order 16 bits of the input data word Y (hereinafter, referred to as “YL”) and outputs a 32-bit product. An adder
103
adds up the output data of the multiplier
101
and the data word ZU retained as high-order 32 bits in the register
105
and outputs a 32-bit sum. An adder
104
adds up the output data of the multiplier
102
and the data word ZL retained as low-order 32 bits in the register
105
and outputs a 32-bit sum. The output data of the adder
103
is stored as the high-order 32 bits in the register
105
, while the output data of the adder
104
is stored as the low-order 32 bits in the register
105
.
In the arithmetic logic unit with such a configuration, the multiplier
101
performs the multiplication XU·YU, the adder
103
adds up the product obtained by the multiplier
101
and ZU that has been stored in the high-order 32 bits in the register
105
, and the register
105
stores the result of the multiply-and-accumulate operation XU·YU+ZU, which is the output of the adder
103
, as its high-order 32 bits.
In the same way, the multiplier
102
performs the multiplication XL·YL, the adder
104
adds up the product obtained by the multiplier
102
and ZL that has been stored as low-order 32 bits in the register
105
, and the register
105
stores the result of the multiply-and-accumulate operation XL·YL+ZL, which is the output of the adder
104
, as its low-order 32 bits.
Suppose the multiply-and-accumulate operation is performed N times with the array elements shown in
FIG. 13
provided as the input data words X and Y to the arithmetic logic unit and with i, or the number of times the data words are input, changed from 0 through N−1. In that case, (x
0
·y
0
+x
2
·y
2
+ . . . +x
2
n−2·y
2
n−2) will be stored as the result of the operation in the high-order 32 bits of the register
105
, while (x
1
·y
1
+x
3
·y
3
+ . . . +x
2
n−1·y
2
n−1) will be stored as the result of the operation in the low-order 32 bits of the register
105
.
Problems to be Solved
However, the conventional arithmetic logic unit must perform the multiply-and-accumulate operation N times and then add together (x
0
·y
0
+x
2
·y
2
+ . . . +x
2
n−2·y
2
n−2) stored in the high-order 32 bits in the register
105
and (x
1
·y
1
+x
3
·y
3
+ . . . +x
2
n−1·y
2
n−1) stored in the low-order 32 bits in the register
105
to obtain (x
0
·y
0
+x
1
·y
1
+x
2
·y
2
+ . . . +x
2
n−2·y
2
n−2+x
2
n−1·y
2
n−1).
To carry out this addition, only the high-order 32 bits of the data stored in the register
105
should be transferred to another register and only the low-order bits of the data stored in the register
105
should be transferred to still another register (or the same register as that receiving the high-order 32 bits). Then, these data bits transferred must be added together.
As can be seen, to obtain a single accumulation result from multiple input data words divided, the conventional arithmetic logic unit needs to perform not only the multiply-and-accumulate operation but also data transfer and addition, thus adversely increasing its processing cycle.
An object of the present invention is providing an arithmetic logic unit that can obtain a single accumulation result from multiple input data words divided without performing the data transfer and addition.
DISCLOSURE OF INVENTION
To solve this problem, an inventive arithmetic logic unit according to the present invention receives (n×M)-bit data words X and Y and outputs a single independent data word Z, where X and Y are each composed of a number n of M-bit data units that are independent of each other. The arithmetic logic unit includes: 1
st
through n
th
multipliers, each multiplying together associated data units with the same digit position of the data words X and Y; 1
st
through n
th
shifters, each being able to perform bit shifting on an output of associated one of the 1
st
through n
th
multipliers; and an adder for adding up outputs of the 1
st
through n
th
shifters. If a sum of the outputs of the 1
st
through n
th
multipliers is obtained as the data word Z, the 1
st
through n
th
shifters perform no bit shifting. But if the outputs of the 1
st
through n
th
multipliers are obtained separately for the data word Z, the 1
st
through n
th
shifters perform a bit-shifting control in such a manner that the outputs of the 1
st
through n
th
multipliers are shifted to respective digit positions not overlapping each other.
In such a configuration, a multiply-and-accumulate operation can be performed with the number of steps reduced. Also, by switching the modes of control performed by the shifter, multiple lines of multiplication can be performed in parallel.
To solve the above problem, an inventive arithmetic logic unit according to the present invention receives (n×M)-bit data words X and Y and outputs a single independent data word Z, where X and Y are each composed of a number n of M-bit data units that are independent of each other. The arithmetic logic unit includes: a register for storing the data word Z; 1
st
through n
th
multipliers, each multiplying together associated data units with the same digit-position of the data words X and Y; and an adder for adding up outputs of the 1
st
through n
th
multipliers and an output of the register and inputting the sum to the register. The arithmetic logic unit performs a sum-of-products operation with the data words X and Y input for multiple cycles.
In such a configuration, even though an increased number of inputs should be provided to a multi-input adder, the increase in circuit size of the adder can be relatively small. Thus, a multiply-and-accumulate operation is realizable with the increase in circuit size minimized.
To solve the above problem, an inventive arithmetic logic unit according to the present invention receives (n×M)-bit data words X and Y and outputs a single independent data word Z, where X and Y are each composed of a number n of M-bit data units that are independent of each-other. The arithmetic logic unit includes: a register for storing the data word Z; 1
st
through n
th
multipliers, each multiplying together associated data units with the same digit position of the data words X and Y; 1
st
through n
th
shifters, each being able to perform bit shifting on an output of associated one of the 1
st
through n
th
multipliers; and an adder for adding up outputs of the 1
st
Kanakogi Tomochika
Nakajima Masaitsu
Malzahn David H.
Matsushita Electric Industrial Co. Ltd
McDermott & Will & Emery
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