Baseband signal processing circuit capable of accurately...

Details Baseband signal processing circuit capable of accurately... Baseband signal processing circuit capable of accurately...

1999-10-18

2003-07-22

Chin, Stephen (Department: 2634)

Pulse or digital communications

Transmitters

Quadrature amplitude modulation

C327S238000

Reexamination Certificate

active

06597747

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a baseband signal processing circuit for processing a baseband signal for digital modulating a carrier wave.
2. Related Background Art
In transmission of a portable telephone in the CDMA system, each of a voice signal and various control signals is converted by a diffusion signal into a digital signal, the digital signal is converted into an analog signal, and a carrier wave is digital modulated (QPSK modulated).
A conventional baseband signal processing circuit will be described with reference to FIG.
4
.
First, a voice signal or the like is converted into a digital signal D by a digital processing circuit
31
. The digital signal D is outputted and supplied to both of a first D/A converter
32
and a second D/A converter
33
. The digital signal D consists of eight bits.
The digital processing circuit
31
outputs a first clock signal C/I and a second clock signal C/Q. The first clock signal C/I is supplied to the first D/A converter
32
and the second clock signal C/Q is supplied to the second D/A converter
33
. Each of the first and second clock signals C/I and C/Q is used to convert the digital signal D into an analog signal. The duty ratio of each of the clock signals is 50%. The first and second clock signals C/I and C/Q are in synchronization with each other and have opposite phases.
In the first D/A converter
32
, the digital signal D is converted into an analog signal at the rising edge of the first clock signal C/I. In the second D/A converter
33
, the digital signal D is converted into an analog signal at the rising edge of the second clock signal C/Q.
As a result, the first D/A converter
32
outputs an analog I signal A/I serving as a first baseband signal. The second D/A converter
33
outputs an analog Q signal A/Q serving as a second baseband signal. The phase of the analog I signal A/I and that of the analog Q signal A/Q are different from each other at 90 degrees.
Each of the analog I signal A/I and the analog Q signal A/Q has a frequency band of about 630 kHz. In order to cut noises at frequencies higher than that, the analog I signal A/I and the analog Q signal A/Q are supplied to a first low-pass filter
34
and a second low-pass filter
35
, respectively. In order to reduce the size of the portable telephone, each of the first and second low-pass filters
34
and
35
takes the form of an active low-pass filter which can be formed in an IC. The analog I signal A/I in which noises at 630 kHz or higher are cut is amplified by a first baseband signal amplifier
36
and then supplied to a first modulator
38
. Similarly, the analog Q signal A/Q in which noises at 630 kHz or higher are cut is amplified by a second baseband signal amplifier
37
and then supplied to a second modulator
39
. Each of the first and second baseband signal amplifiers
36
and
37
takes the form of an operational amplifier.
In order to set each of the level of the analog I signal A/I to be supplied to the first modulator
38
and the level of the analog Q signal A/Q to be supplied to the second modulator
39
to a predetermined level (for example, 1 volt), the amplification degree of each of the first and second baseband signal amplifiers
36
and
37
can be changed.
A first carrier wave&PHgr;/I is supplied to the first modulator
38
and a second carrier wave&PHgr;/Q is supplied to the second modulator
39
. The phase of the first carrier waved&PHgr;/I and that of the second carrier wave&PHgr;/Q are different from each other by 90 degrees. The first and second carrier waves&PHgr;/I and &PHgr;/Q are obtained by a phase shifter
41
on the basis of an original carrier wave (its frequency is about 130 MHz) outputted from a carrier oscillator
40
.
The first carrier waves&PHgr;/I is PSK modulated by the analog I signal A/I and the second carrier wave&PHgr;/Q is PSK modulated by the analog Q signal A/Q. The PSK modulated two signals are added by an adder
42
, thereby obtaining a signal which has been QPSK modulated as a whole. The resultant signal is frequency converted to a transmission signal of about 800 MHz to 900 MHz by a frequency converter (not shown), further, a predetermined process is performed, and a resultant signal is transmitted from an antenna (not shown) to a base station.
In the conventional baseband signal processing circuit described above, the phase difference between the analog I signal outputted from the first D/A converter
32
and the analog Q signal outputted from the second D/A converter
33
is set to 90 degrees. It happens, however, that the phase of the first clock signal C/I or second clock signal C/Q is deviated or the phase difference between the analog I signal A/I and the analog Q signal A/Q is deviated from 90 degrees due to a phase error (for example, due to different phase characteristics of the low-pass filters
34
and
35
) in the transmission paths from the low-pass filters
34
and
35
to the adder
42
.
In a state where the phase difference between the analog I signal A/I and the analog Q signal A/Q is deviated from 90 degrees, the first and second carrier waves&PHgr;l and &PHgr;
2
are PSK modulated. As a result, the reception sensitivity on the reception side deteriorates, a bit error occurs at the time of demodulation on the reception side, and a problem such that a signal cannot be normally transmitted and received arises.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a baseband signal processing circuit capable of accurately setting the phase difference between an analog I signal A/I serving as a first baseband signal and an analog Q signal A/Q serving as a second baseband signal to 90 degrees.
In order to achieve the object, there is provided a baseband signal processing circuit of the invention comprising: a first D/A converter for receiving a digital signal and a first clock signal which is used to convert the digital signal into an analog signal and outputting a first baseband signal; and a second D/A converter for receiving the digital signal and a second clock signal which is used to convert the digital signal into an analog signal and outputting a second baseband signal, wherein the first and second clock signals are synchronized with each other and a time interval between rise time or fall time of the first clock signal and rise time or fall time of the second clock signal is changeable.
According to the baseband signal processing circuit of the invention, the duty ratio of either the first clock signal or the second clock signal is changeable.
According to the baseband signal processing circuit of the invention, the digital signal, the first clock signal, and the second clock signal are outputted from a digital processing circuit, a duty adjusting circuit is provided either between the digital processing circuit and the first D/A converter or between the digital processing circuit and the second D/A converter, and the first clock signal or the second clock signal is supplied to the first D/A converter or the second D/A converter via the duty adjusting circuit.
There is also provided a baseband signal processing circuit of the invention comprising: a first D/A converter for receiving a digital signal and a first clock signal which is used to convert the digital signal into an analog signal and outputting a first baseband signal; and a second D/A converter for receiving the digital signal and a second clock signal which is used to convert the digital signal into an analog signal and outputting a second baseband signal, wherein the first and second clock signals are synchronized with each other and the phase difference between the first clock signal and the second clock can be changed.


REFERENCES:
patent: 5387883 (1995-02-01), Ueda
patent: 5396296 (1995-03-01), Gallagher
patent: 5548253 (1996-08-01), Durrant
patent: 5886584 (1999-03-01), Tanai et al.
patent: 5896053 (1999-04-01), Prentice
patent: 5930689 (1999-07-01), Wilhite et al.
patent: 6198777 (2001-03-01), Feher

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