Stacked microelectronic dies and methods for stacking...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

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Details

C257S686000

Reexamination Certificate

active

06607937

ABSTRACT:

TECHNICAL FIELD
The present invention relates to stacked microelectronic dies and methods for stacking microelectronic dies.
BACKGROUND OF THE INVENTION
Packaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic device mounted to a substrate and encased in a plastic protective covering. The device includes functional features, such a memory cells, processor circuits, and interconnecting circuitry. The device also typically includes bond pads electrically coupled to the functional features. The bond pads are coupled to pins or other types of terminals that extend outside the protective covering for connecting the microelectronic device to buses, circuits and/or other microelectronic assemblies.
One conventional approach to reducing the surface area occupied by packaged microelectronic devices in compact electronic products is to stack one packaged device on another packaged device having an identical configuration. For example, as shown in
FIG. 1
, an upper packaged microelectronic device
20
b
can be stacked on a lower packaged microelectronic device
20
a
(collectively referred to as packaged devices
20
) and the assembly of packaged devices
20
can be attached to a printed circuit board (PCB)
30
. Each packaged device
20
typically includes a die
24
encased in an encapsulant
23
. Each die
24
has a plurality of die bond pads
25
connected to pins
43
that extend outside the encapsulant
23
. Corresponding pins
43
of each packaged device
20
are connected directly to each other and to corresponding bond pads
31
on the PCB
30
. The packaged devices
20
are also connected to each other by attaching an adhesive
11
between the encapsulant
23
of the lower packaged device
20
a
and the encapsulant
23
of the upper packaged device
20
b.
In another conventional arrangement shown in
FIG. 2
, two identical packaged devices
120
(shown as a lower packaged device
120
a
and an upper packaged device
120
b
) are connected to each other and to a PCB
130
with solder balls
143
. Each packaged device
120
can include a die
124
mounted to a substrate PCB
140
and encased with an encapsulant
123
. Each die
124
has die bond pads
125
connected with wire-bonds
126
to corresponding bond pads
131
a
of the substrate PCB
140
. The bond pads
131
a
are connected to solder ball pads
131
b
with circuitry internal to the support PCB
140
. The solder balls
143
connect the solder ball pads
131
b
of the upper package
120
b
to the solder ball pads
131
b
of the lower package
120
a
. Additional solder balls
143
connect the lower package
120
a
to corresponding bond pads
131
c
of the PCB
130
.
One drawback with the conventional arrangements described above with reference to
FIGS. 1 and 2
is that the stacked packaged devices are connected to each other. Accordingly, it can be difficult to remove and replace one packaged device without removing or damaging the other. Furthermore, this arrangement can require several tests to confirm that the packaged devices remain operable after each manufacturing step. For example, the packaged devices may be tested individually before they are coupled, then tested again after they are coupled to each other, and then tested yet again after the coupled packaged devices are mounted to the PCB. Each test can add to the time required to complete the final product, and can accordingly reduce the efficiency of the manufacturing process.
SUMMARY
The present invention is directed toward microelectronic package assemblies and methods for stacking packaged microelectronic devices. A method in accordance with one aspect of the invention includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, and coupling the first packaged device to a first portion of the support member circuitry. The first packaged microelectronic device includes a first microelectronic die at least partially encased in a first encapsulant to define a first package configuration. The method further includes positioning at least proximate to the first packaged device a second packaged microelectronic device having a second microelectronic die at least partially encased in a second encapsulant to define a second package configuration different than the first package configuration. The second packaged device is electrically coupled to a second portion of the support member circuitry, and the first packaged device is positioned between the support member and the packaged device. In a further aspect of this embodiment, the second packaged microelectronic device can be connected to the support member without being connected to the first packaged microelectronic device. Accordingly, the second packaged microelectronic device package can be removed from the support member without removing the first packaged microelectronic device.
The invention is also directed toward an assembly of packaged microelectronic devices. The assembly can include a support member having support member circuitry, and a first packaged microelectronic device connected to at least one of the support member and the support member circuitry. The first packaged device has a first microelectronic die at least partially encased in a first encapsulant to define a first package configuration. The assembly can further include a second packaged microelectronic device connected to at least one of the support member and the support member circuitry with the first packaged device positioned between the support member and the second packaged device. The second packaged device has a second microelectronic die at least partially encased in a second encapsulant to define a second package configuration different than the first package configurations, and the second packaged device can be connected directly to the support member without being connected to the first packaged device.


REFERENCES:
patent: 5128831 (1992-07-01), Fox, III et al.
patent: 5222014 (1993-06-01), Lin
patent: 5252857 (1993-10-01), Kane et al.
patent: 5323060 (1994-06-01), Fogal et al.
patent: 5776797 (1998-07-01), Nicewarner, Jr. et al.
patent: 5793101 (1998-08-01), Kuhn
patent: 5883426 (1999-03-01), Tokuno et al.
patent: 5946553 (1999-08-01), Wood et al.
patent: 5986209 (1999-11-01), Tandy
patent: 5990566 (1999-11-01), Farnworth et al.
patent: 6020624 (2000-02-01), Wood et al.
patent: 6020629 (2000-02-01), Farnworth et al.
patent: 6028365 (2000-02-01), Akram et al.
patent: 6051878 (2000-04-01), Akram et al.
patent: 6072233 (2000-06-01), Corisis et al.
patent: 6072236 (2000-06-01), Akram et al.
patent: 6100594 (2000-08-01), Fukui et al.
patent: 6121676 (2000-09-01), Solberg
patent: 6153924 (2000-11-01), Kinsman
patent: 6154366 (2000-11-01), Ma et al.
patent: 6160718 (2000-12-01), Vakilian
patent: 6175149 (2001-01-01), Akram
patent: 6212767 (2001-04-01), Tandy
patent: 6222265 (2001-04-01), Akram et al.
patent: 6225689 (2001-05-01), Moden et al.
patent: 6228548 (2001-05-01), King et al.
patent: 6235554 (2001-05-01), Akram et al.
patent: 6258623 (2001-07-01), Moden et al.
patent: 6261865 (2001-07-01), Akram
patent: 6262895 (2001-07-01), Forthun
patent: 6281577 (2001-08-01), Oppermann et al.
patent: 6294839 (2001-09-01), Mess et al.
patent: 6297547 (2001-10-01), Akram
patent: 6303981 (2001-10-01), Moden
U.S. patent application Ser. No. 09/634,056, Jiang et al.
“3-D IC Packaging.”3-D IC Packaging Industry News.May 1998. http://www.semiconductor.net/semiconductor/archive/May98/docs/ind_news2.html (Dec. 30, 1999).
Plöss1, A. and Kräuter, G., “Wafer direct bonding: tailoring adhesion between brittle materials,”Materials Science and EngineeringR25(1-2): pp. 1-88, 1999.
U.S. patent application Ser. No. 09/606,432, Moon, filed Jun. 28, 2000.
U.S. patent application Ser. No. 09/944,723, Moon, filed Aug. 30, 2001.

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