Nonvolatile semiconductor memory device capable of reducing...

Details Nonvolatile semiconductor memory device capable of reducing... Nonvolatile semiconductor memory device capable of reducing...

2002-01-28

2003-04-01

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S185330

Reexamination Certificate

active

06542410

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device in which write is executed by means of channel hot electrons and an erase method therefor.
Conventionally, there has been an ETOX (EPROM THIN OXIDE: trademark of Intel Corp.) as a flash memory (batch erase type memory) used most generally.
FIG. 12
shows a schematic sectional view of this ETOX type flash memory cell
8
. As is apparent from
FIG. 12
, a floating-gate
5
is formed via a tunnel oxide film
4
on a source
1
, a drain
2
and a substrate (well)
3
located between the source and the drain. Further, a control gate
7
is formed on the floating-gate
5
via a layer insulation film
6
.
The principle of operation of the ETOX type flash memory cell
8
will now be described. As shown in the following Table 1, during write, a voltage Vpp (10 V, for example) is applied to the control gate
7
, a reference voltage Vss (0 V, for example) is applied to the source
1
, and a voltage of 6 V is applied to the drain
2
. With this arrangement, a large amount of current flows through the channel layer to generate channel hot electrons in a portion of a high electric field on the drain
2
side, and the electrons are injected into the floating-gate
5
. Consequently, the threshold voltage of the memory cell
8
rises to execute write into the memory cell
8
.
FIG. 13
shows threshold voltage distributions in a written state and an erased state. As shown in
FIG. 13
, the threshold voltage of the written memory cell
8
becomes equal to or higher than 5 V.
TABLE 1
Control
Gate 7
Drain 2
Source 1
Substrate 3
Write
10 V
6 V/ Open
0 V
0 V
Erase
−9 V
Open
6 V
0 V
Read
 5 V
1 V
0 V
0 V
During erase, by applying a voltage Vnn (−9 V, for example) to the control gate
7
, applying a voltage Vpe (6 V, for example) to the source
1
and making the drain
2
open, intense electric field occurs in the tunnel oxide film
4
located between the source
1
and the floating-gate
5
. Then, electrons are extracted from the floating-gate
5
toward the source
1
by the Fowler-Nordheim (FN) tunneling phenomenon, lowering the threshold voltage of the memory cell
8
. Consequently, as shown in
FIG. 13
, the threshold voltage of the erased memory cell
8
becomes 1.5 V to 3 V.
During read, a voltage of 1 V is applied to the drain
2
, and a voltage of 5 V is applied to the control gate
7
. In this case, when the memory cell
8
is in the erased state and has a low threshold voltage, a current flows through the memory cell
8
to determine that the state is “1”. When the memory cell
8
is in the written state and has a high threshold voltage, no current flows through the memory cell
8
to determine that the state is “0”.
On the basis of the principle of operation as described above, the write, erase and read of the memory cell
8
are executed. During the erase of the actual nonvolatile semiconductor memory device, the erase is executed in batch processing of comparatively large blocks of, for example, 64 kB. In the above case, the threshold voltages of the memory cells inside the block to be erased include those in the written state (threshold voltage is not lower than 5 V in
FIG. 13
) and those in the erased state (threshold voltage is 1.5 V to 3 V in FIG.
13
), which exist in a mixed state. Then, in order to put the threshold voltages of all the memory cells
8
that are to be erased within a specified threshold voltage distribution (1.5 V to 3 V, for example), a complicated algorithm is used for the batch erase.
During erase, it is a key point to prevent the occurrence of a memory cell in an overerased (excessively erased) state in which the threshold voltage becomes equal to or lower than 0 V due to the application of an erase pulse to a memory cell that originally has a low threshold voltage and the application of an erase pulse to a memory cell in which the threshold voltage is lowered fast due to variations in erase characteristics.
Upon the occurrence of the memory cell in the overerased state, if it is attempted to apply a specified voltage (3.0 V, for example, in the case of erase verify) to the word line connected to the control gate
7
of the selected memory cell while setting a voltage of 0 V on the word line connected to the control gate
7
of the non-selected memory cell during, for example, write verify or erase verify and to execute verify based on the presence or absence of a cell current flowing through the non-selected memory cell, then a cell current flows also through the memory cell in the overerased state that exists among the non-selected memory cells. Therefore, it is unable to correctly verify the presence or absence of a cell current in the selected memory cells. That is, since the threshold voltage cannot be verified, the write and erase cannot correctly be executed. Therefore, if the memory cell in the overerased state occurs, then the reliability of the nonvolatile semiconductor memory device is impaired.
FIG. 14
shows one example of the erase algorithm for preventing the occurrence of the memory cell in the overerased state. When the erase operation is started in
FIG. 14
, pre-erase write for preventing the overerase is first executed in all the memory cells in step S
1
. This pre-erase write operation is the same as the ordinary write operation described hereinabove and executed as follows. That is, the voltages shown in Table 1 are applied to the sources
1
and the substrates (wells)
3
of all the memory cells
8
in the block to be subjected to erase. Then, the memory cells
8
are sequentially selected for the application of the voltages shown in Table 1 to the control gates
7
and the drains
2
.
In step S
2
, the write verify is executed. That is, the threshold voltage value of each memory cell
8
is verified. It is determined in step S
3
whether or not the verify result is acceptable, i.e., it is determined whether or not the threshold voltage values of all the memory cells
8
are not lower than the specified value (5.0 V) that represents the written state. As a result, the program flow returns to the step S
1
to repeat the pre-erase write when it is unacceptable or proceeds to step S
4
when it is acceptable. In this case, the write verify operation has the same application voltages to the drain
2
, the source
1
and the substrate (well)
3
as in the read operation in Table 1 and also has an application voltage of 5.0 V to the control gate
7
. Thus, the voltage of 5.0 V is applied via the word line to the control gate
7
of the selected memory cell
8
in which the write verify is executed, while a voltage of 0 V is applied to the control gate
7
of the non-selected memory cell
8
to determine whether or not a cell current flows through the selected memory cell
8
. Then, it is determined that the threshold voltage of the selected memory cell
8
is not lower than 5.0 V and the written state is established when no cell current flows through the selected memory cell
8
. In contrast to this, when a cell current flows, it is determined that the threshold voltage of the selected memory cell
8
is lower than 5.0 V, and the pre-erase write is executed again. Subsequently, this operation is repeated, and the pre-erase write is ended when the threshold voltages of all the memory cells to be erased become equal to or higher than 5.0 V.
In step S
4
, the erase pulse is applied. The pulse width of the erase pulse in the above case is set to, for example, 10 ms, which is shorter than the erase time required for changing the written state into the erased state so that a number of memory cells, in which the threshold voltage is lowered fast attributed to the variations in the erase characteristics, is not put into the overerased state. Then, by putting the drain
2
of the memory cell
8
to be subjected to erase into an open state, making the substrate (well)
3
have a voltage of 0 V, applying an erase pulse of −9 V to the control gate
7
and applying an erase pulse of 6 V to the source
1
, the erase is executed in b

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