Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1999-04-23
2003-07-01
Sikes, William L. (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C257S072000, C349S042000
Reexamination Certificate
active
06587161
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to liquid crystal display devices for use in, for example, monitors for personal computers and OA (office automation) and FA (factory automation) equipment, and display panels for portable information terminals.
BACKGROUND OF THE INVENTION
Conventionally, liquid crystal display devices using nematic liquid crystals have been widely used as segment type liquid crystal display devices for use in watches and electronic calculators. In recent years, such a liquid crystal display device has expanded its market and been used as various types of displays for word processors, personal computers, navigation systems, etc., because of its thin, light weight, low power consuming characteristics. In particular, an active matrix liquid crystal display device in which active elements such as TFTs (thin film transistors) are used as switching elements and pixels are arranged in a matrix, has been noted.
Compared to, for example, a CRT (cathode ray tube), the above-mentioned liquid crystal display devices have advantages that they can be made much thinner (in depth), achieve a full color display easily, and consume less power. Therefore, such liquid crystal display devices are suitably used as displays of notebook type personal computers, portable television sets, digital cameras, digital video cameras, and so on.
A conventional transmissive type active matrix liquid crystal display device includes a light transmitting active matrix substrate, a counter substrate having a common electrode formed thereon, and a liquid crystal. An active matrix circuit constituted by a TFT is formed on the active matrix substrate. The counter substrate is disposed to face the active matrix substrate, and a liquid crystal is sandwiched between the active matrix substrate and the counter substrate.
FIG. 11
is a circuit diagram showing schematically an example of the active matrix circuit on the active matrix substrate. A plurality of pixel electrodes
31
are arranged in a matrix on the active matrix substrate. Usually, several hundred pixel electrodes
31
are arranged respectively in rows and columns.
Besides, a common electrode
32
is formed on the counter substrate so that the common electrode
32
faces the pixel electrodes
31
with a liquid crystal layer therebetween. A voltage is applied to the liquid crystal layer by the pixel electrodes
31
and common electrode
32
. In general, the common electrode
32
is formed on the substantially entire surface of the counter substrate.
Moreover, TFTs
33
as active elements functioning as switching means for selectively driving the pixel electrodes
31
are formed on the active matrix substrate and connected to the pixel electrodes
31
. Furthermore, in order to provide a color display, a color filter layer (not shown) including, for example, red, green and blue filters is placed on the counter substrate or the active matrix substrate.
Scanning lines
34
are connected to the gate electrodes of the TFTs
33
, while signal lines
35
are connected to the source electrodes thereof. The scanning lines
34
and signal lines
35
are arranged such that they run around the pixel electrodes
31
arranged in a matrix and cross each other at right angles. By inputting gate signals through the scanning lines
34
, the TFTs
33
are driven under control. Further, when the TFTs
33
are driven, data signals are input to the pixel electrodes
31
through the signal lines
35
. Incidentally, scanning signal input terminals
34
a
are connected to the end sections of the scanning lines
34
, and data signal input terminals
35
a
are connected to the end sections of the signal lines
35
.
Besides, the drain electrodes of the TFTs
33
are connected to the pixel electrodes
31
and the accumulation capacitors
36
. The accumulation capacitors
36
are connected to reference signal lines
37
, respectively. The accumulation capacitors
36
perform the function of maintaining a voltage applied to the liquid crystal layer.
In the active matrix liquid crystal display device as described above, the liquid crystal layer sandwiched between the active matrix substrate and counter substrate has a thickness of usually between 4.3 and 4.5 &mgr;m on average, and a liquid crystal capacitor is formed by the pixel electrodes
31
, common electrodes
32
and liquid crystal layer. Additionally, the accumulation capacitors
36
are connected to the liquid crystal capacitor in parallel.
In the above-mentioned structure, as illustrated in
FIG. 7
, the liquid crystal capacitor and the accumulation capacitor
36
are connected to the reference signal line
37
in series. Here, the capacitance of the liquid crystal capacitor is represented by Clc, and the capacitance of the accumulation capacitor
36
is represented by Cs. Then, the series capacitance of the liquid crystal capacitor and the accumulation capacitor
36
per pixel is given by (Clc×Cs)/(Clc+Cs).
For instance, in the case of a liquid crystal display device with a 13.3-inch display and XGA (extended graphics array) of (1024×768), the series capacitance per pixel is around 0.33×Clc. When N pieces of such a series capacitance are provided for each reference signal line
37
, the total load capacitance per reference signal line
37
is around 0.33×N×Clc.
Such a load capacitance would cause a signal delay. In order to reduce the signal delay, a connecting line
38
for connecting the reference signal lines
37
to each other may be provided as shown in FIG.
11
.
Here, the structure of the TFT
33
will be explained in great detail.
FIG. 10
is a cross sectional view showing a schematic structure in the vicinity of the TFT
33
. A gate electrode
40
is formed on a transparent insulating substrate
39
, and a gate insulating film
41
is formed to cover the gate electrode
40
. A semiconducting film
42
is formed on the gate electrode
40
with the gate insulating film
41
therebetween. A channel protecting film
43
is formed at the top center of the semiconducting film
42
. A source electrode
44
s
made of a microcrystal n
+
silicone layer is provided on the source side of the channel protecting film
43
and semiconducting film
42
. Similarly, a drain electrode
44
d
made of a microcrystal n
+
silicone layer is provided on the drain side thereof.
A metallic layer
45
s
serving as a source line is connected to the source electrode
44
s
, while a metallic layer
45
d
for forming a drain line is connected to the drain electrode
44
d.
The surface of the TFT
33
having the abovementioned structure is covered with an inter-layer insulating film
46
. Further, a transparent conductive film for forming a pixel electrode
31
is placed on the inter-layer insulating film
46
. The pixel electrode
31
is connected to the metallic layer
45
d
as the drain line of the TFT
33
through a contact hole
47
. Moreover, on the pixel electrodes
31
, although it is not shown in the drawings, an alignment film for aligning the liquid crystal is formed substantially uniformly over the entire display area.
As the inter-layer insulating film
46
, an inorganic thin film such as SiN has been conventionally used. The SiN film is deposited with a film thickness of more than around 300 nm by, for example, a CVD (chemical vapor deposition) method.
Moreover, as an example of a liquid crystal display device having a structure different from the above-mentioned structure of the liquid crystal display device, Japanese laid-open patent publication No. (Tokukaihei) 7-128687 (published on May 19, 1995) discloses a liquid crystal display device in which the signal lines are formed on the counter substrate. In this liquid crystal display device, since the scanning lines and the signal lines are formed on different substrates, they do not intersect each other on a single substrate. As a result, the rate of occurrence of defects due to a short circuit between the scanning line and the signal line is reduced, thereby achieving an improved yield.
FIG. 12
is a circu
Fujiwara Kouji
Inoue Naoto
Tagusa Yasunobu
Tanaka Keiichi
Yamamoto Tomohiko
Nguyen Dung
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
Sikes William L.
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