Process for device fabrication

Details Process for device fabrication Process for device fabrication

1997-07-31

2003-05-20

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

Reexamination Certificate

active

06566224

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices.
2. Discussion of the Related Art
The continuing desire for greater integration of circuits requires ever-shrinking size and spacing of devices on the circuits. Current methods for electrically isolating the numerous devices, such as the use of field oxides or trench oxides, are not always sufficient. One widely-used field oxide isolation technique is local oxidation of silicon (LOCOS). In LOCOS, an oxidation barrier (typically silicon nitride) is formed over the locations on the substrate where active devices are to be formed. The substrate is then oxidized to form silicon dioxide at the unmasked areas, the silicon oxide isolating active silicon regions.
LOCOS has several limitations, however. The silicon dioxide generally grows under the barrier layer (forming what is known as a bird's beak), and thereby encroaches into the active regions. The encroachment typically increases the required spacing between devices and is therefore detrimental to attainment of higher device density. And attempts to limit the bird's beak by forming a thinner oxide layer generally result in a lower isolation threshold voltage than desired. In addition, it is possible for LOCOS to add undesirable topography to the IC surface. The silicon dioxide necessarily occupies a greater volume than the silicon from which the oxide is formed, because the silicon dioxide molecules are larger than the silicon atoms. Thus, the silicon dioxide rises above the surface of the adjacent silicon active regions, forming steps. These steps create problems in the process of forming gate structures by complicating both lithography and etching steps. The steps also affect the reliability of the conductor layer. Moreover, it is possible for the height of the steps to exceed the height acceptable for sub-micron lithographic processes, such that the steps interfere with subsequent processing steps.
A more recent isolation technique, which avoids some of the problems of LOCOS, is shallow trench isolation (STI). STI involves the formation of trenches in the surface of the silicon substrate, and filling of the trenches with a silicon oxide, such as thermal or deposited silicon dioxide. STI is capable of providing relatively thick isolation oxides that extend into the substrate with little or no encroachment into the active regions, and which have an upper surface that is relatively coplanar with adjacent areas. STI thus offers improved isolation, greater packing density, and better planarity than LOCOS, all of which contribute to greater device density.
However, STI also suffers from some problems. Parasitic leakage paths are generally created due to the proximity of a semiconductor device to the sharp corners of a trench. The effect is reflected in
FIG. 1
, which shows a silicon substrate
10
, trench isolation
12
, gate oxide layer
14
, and gate layer
16
. A parasitic leakage path is created across the length of a transistor along a sharp trench corner, e.g., corner
20
, due to an increased gate electric field near the corner
20
. Processing often furthers this problem by sharpening the trench corners and/or thinning the gate dielectric near the corners. The leakage is increased where the gate layer
16
extends into the trench
12
, forming what is known as gate wrap-around
18
, such wrap-around
18
formed by typical wet etch steps used in device fabrication. Several solutions for these problems have been proposed. U.S. Pat. Nos. 5,521,422 and 5,433,794 disclose the use of spacers around the trench material. The spacers reduce both gate wrap-around (
18
) and the effect of sharp corners (
20
) along the top surface of the trench material. U.S. Pat. No. 5,387,540 discloses formation of a silicon dioxide layer over the trench material to increase the thickness of the gate dielectric near the top surface corners of the trench material. Thus, the inventors of these patents looked for ways to compensate for sharp corners (
20
), not to eliminate them.
The contribution of sharp corners at the area where the trench material meets the lower surface of the gate oxide, i.e., corner
20
, to leakage current has been studied. See, e.g., Geissler et al., “A New Three-Dimensional MOSFET Gate-Induced Drain Leakage Effect in Narrow Deep Submicron Devices,” IEDM Tech. Dig., 1991, p.839; Watanabe et al. “Corner-Rounded Shallow Trench Isolation Technology to Reduce the Stress-Induced Tunnel Oxide Leakage Current for Highly Reliable Flash Memories,” IEDM Tech. Dig., 1996, p.833; and Chatterjee et al., “A Shallow Trench Isolation using LOCOS Edge for Preventing Corner Effects for 0.25/0.18 &mgr;m CMOS Technologies and Beyond,” IEDM Tech. Dig., 1996, p.829. However, while calculations directed to the beneficial effects of rounded corners have been made in these articles, attempts, such as that of Chatterjee, to actually round the corners have been unsatisfactory.
Specifically, as reflected in
FIGS. 1
the method of Chatterjee et al. involves formation, on a silicon substrate
21
, of nitride barrier regions
22
; formation of oxide regions
23
by LOCOS (
FIG. 1
b
); removal of the oxide regions
23
; application of silicon dioxide to form spacers
24
around the nitride barrier regions
22
(
FIG. 1
c
); etching of the spacers
24
; and then etching of the trenches
24
for STI (
FIG. 1
d
). This complex method is not suitable for most commercial applications, for which simple, cost-effective processes are desired. A similar method involving a complex LOCOS/STI combination is taught by U.S. Pat. No. 5,468,676, which discusses the problem of trench sidewall leakage related to the effects of sharp corner
20
. An earlier Chatterjee et al. article, “A Shallow Trench Isolation Study for 0.25/0.18 &mgr;m CMOS Technologies and Beyond,” 1996 IEEE Symposium on VLSI Technology, Digest of Technical Papers, also presents an STI process. This earlier Chatterjee et al. article discusses a step of thermal oxidation at 900° C. before filling the etched trench with silicon dioxide. However, the authors of this earlier article did not recognize a way to overcome the problems of sharp corner
20
, and disclosed a method that produced a minor amount of rounding insufficient to reduce or eliminate the corner problems. The later Chatterjee article specifically states that to avoid detrimental sharp corner effects of corner
20
, both the complex LOCOS/STI combination and the 900° C. thermal oxidation must be performed (see section II of the later article).
Thus, while problems associated with a sharp silicon corner
20
have been recognized, solutions have focused on compensating for the sharp corner
20
. A simple solution for the problem of the sharp silicon corner
20
is desired.
SUMMARY OF THE INVENTION
It has been found to be possible to round problematic sharp corners in STI structures in a relatively simple manner. Specifically, the corners of the silicon of the active regions, at the point where the trench oxide meets the lower surface of a stress relief or other region disposed directly on a silicon substrate, are desirably rounded by a single oxidation step. The extent of rounding that substantially reduces problems caused by a sharp corner will vary, depending primarily on the amount of gate wrap-around. The oxidation step of the invention advantageously provides a radius of curvature of about 30 to about 80 nm. The oxidation step is advantageously performed in an environment and for a time and temperature that results in formation of a silicon dioxide layer about 50 nm to about 150 nm thick on a blank silicon wafer (hereafter referred to as an equivalent oxide layer). Advantageously, the temperature for oxidation ranges from about 950° C. to about 1100° C., the lower end of this range being more useful with wet oxidation (i.e., water vapor present), and the higher end with dry oxidation. The oxidation temperature affects the time required to attain the selected equivalent oxide layer, and the extent of rounding

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