Semiconductor memory device with improved setup time and...

Details Semiconductor memory device with improved setup time and... Semiconductor memory device with improved setup time and...

2001-07-18

2003-05-27

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230030, C365S233100

Reexamination Certificate

active

06570812

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device for introducing therein an address signal in synchronization with an external clock.
2. Description of the Background Art
FIG. 13
is a timing chart showing the relation between an external clock ext.CLK and an external address ext.Add that are input to a conventional synchronous dynamic random access memory (SDRAM).
Referring to
FIG. 13
, the timing of introducing the external address ext.Add is defined with respect to the rising edge of the external clock ext.CLK. In
FIG. 13
, tIS indicates setup time, and tIH indicates hold time.
The input address passes through an input buffer including a comparator and the like, which is located at a first input stage. In the input buffer, the input address is converted into a signal INTA having an appropriate internal level. The signal INTA is latched for a fixed period in an address latch. A trigger signal of the address latch is an internal clock ZCLKF produced from the clock ext.CLK. Although depending also on the circuit characteristics of the address latch, the setup time tIS and hold time tIH are determined mainly according to the propagation characteristics of the signal INTA and internal clock ZCLKF.
The propagation characteristics of these signals depend on the distance from an address pad and a clock pad to the address latch. Accordingly, the position of the address latch within the chip is important.
FIG. 14
is a diagram illustrating the pad arrangement and memory-array arrangement of a conventional general SDRAM.
Referring to
FIG. 14
, the SDRAM
500
includes memory banks A to D. The memory banks A to D are arranged in two rows by two columns. Each memory bank has a row decoder RD located in the center thereof, and column decoder bands CPW located on both sides of the row decoder RD so as to correspond to respective memory arrays. More specifically, the bank A includes memory arrays
501
and
502
. The bank B includes memory arrays
503
and
504
. The bank C includes memory arrays
505
and
506
. The bank D includes memory arrays
507
and
508
.
The SDRAM
500
has a central region extending along the line connecting the respective middle points of the shorter sides of the chip. The SDRAM
500
includes an address pad train
514
, a control-signal pad train
516
, and a DQ pad train
518
in the central region.
The DQ pad
518
is located between the banks A and B. The address pad train
514
and control-signal pad train
516
are located between the banks C and D.
A first input stage
512
is provided corresponding to the pads receiving an input signal out of pads
510
of these pad trains. The pads of the address pad train
514
correspond to an address signal on a bit-by-bit basis. More specifically, the pads of the address pad train
514
respectively correspond to address signals A
4
, A
3
, A
5
, A
2
, A
6
, A
1
, A
7
, A
0
, A
8
, A
10
, A
9
, BA
1
, A
11
, BA
0
, A
12
sequentially from its end. The address thus input from the address pad train
514
passes through the first input stage
512
, and is input to an address latch circuit
538
as a signal INTA.
The control-signal pad train
516
includes a pad for receiving a clock signal CLK. The clock CLK is input through a first input stage to the address latch circuit
538
as an internal clock ZCLKF.
FIG. 15
is a diagram showing the structure of the address latch circuit
538
of FIG.
14
.
Referring to
FIG. 15
, the address latch circuit
538
includes address latches
538
.
0
to
538
.
14
respectively corresponding to the bits of the address signal. More specifically, the address latches
538
.
0
to
538
.
12
receive address signals INTA_A
0
to INTA_A
12
, and output signals ADD<
0
> to ADD<
12
>, respectively. The address latches
538
.
13
and
538
.
14
receive address signals INTA_BA
0
and INTA_BA
1
, and output signals BADD<
0
> and BADD<
1
>, respectively.
The address latch circuit
538
further includes an inverter
540
for receiving the internal clock signal ZCLKF and generating a clock signal CLKA serving as a reference for introducing the internal address signal INTA to each address latch. The inverter
540
drives an internal node having a plurality of clock input nodes of the address latches connected thereto and thus having large load capacitance.
FIG. 16
is a circuit diagram showing the structure of the address latch
538
.
0
in FIG.
15
.
Referring to
FIG. 16
, the address latch
538
.
0
includes an inverter
552
for receiving and inverting the clock signal CLKA, an inverter
554
for receiving and inverting the signal INTA, and P-channel MOS transistors
556
,
558
and N-channel MOS transistors
560
,
562
connected in series between the power supply potential and the ground potential. The P-channel MOS transistors
556
and
558
receive the output of the inverter
554
and the clock signal CLKA at their gates, respectively. The N-channel MOS transistors
560
and
562
receive the outputs of the inverters
552
and
554
at their gates, respectively.
The address latch
538
.
0
further includes inverters
564
,
568
having their inputs connected to the drain of the N-channel MOS transistor
560
, a clocked inverter
570
for receiving the output of the inverter
568
for feedback to the input of the inverter
568
, and an inverter
566
for receiving the output of the inverter
564
and outputting the signal ADD. The clocked inverter
570
is activated in response to activation of the clock signal CLKA.
Referring back to
FIG. 14
, the address pad train
514
is arranged in line, and therefore has a long train length. Provided that all address latches are collectively located at a single location as in the address latch circuit
538
, the length of a path from the first input stage to the address latch circuit
538
, i.e., a transmission path of the signal INTA, is significantly different from address bit to address bit, resulting in variation in setup time and hold time among the address bits.
Note that it is also possible to arrange the address latches separately on a pad-by-pad basis. In this case, however, the propagation time of the internal clock signal ZCLKF becomes different from address bit to address bit, also resulting in variation in setup time and hold time among the address bits.
In order to solve these problems in principle, it is primarily important to reduce the length of the address pad train. One possible method thereof is to arrange the address pads in two or more trains.
However, in the general structure of
FIG. 14
in which the memory banks are arranged in two rows by two columns, arranging the address pads in two trains increases the width of the peripheral circuit band extending along the line connecting the respective middle points of the shorter sides of the chip, thereby significantly increasing the length of the shorter side of the chip. As a result, the number of chips obtained per wafer is significantly reduced, resulting in increased costs of the semiconductor memory device. Therefore, arranging the address pads in multiple trains has been substantially impossible at least in a chip in which the memory banks are arranged in two rows by two columns, i.e., a chip for mass production.
Conventionally, dynamic random access memories (DRAMs) including synchronous dynamic random access memories (SDRAMs) generally have a 2
n
-bit storage capacity. In order to realize this capacity, the memory arrays or banks of the DRAM are generally arranged in two by two, i.e., two rows by two columns.
Developing a new DRAM with a fourfold memory capacity in a 3-year cycle is a conventional trend. However, it is becoming technically difficult to improve the memory capacity as such. In the meantime, with expansion of the information and communication industry such as widespread use of the Internet, there is an active demand on the market for the improved memory capacity. In such circ

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