Static information storage and retrieval – Floating gate – Data security
Reexamination Certificate
2001-09-21
2003-07-29
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Data security
C365S185030, C365S185110, C365S185120, C365S185090, C365S185290
Reexamination Certificate
active
06600676
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-297443, filed Sep. 28, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to an electrically rewritable nonvolatile semiconductor memory device.
2. Description of the Related Art
A NAND flash memory using an EEPROM as an electrically rewritable nonvolatile semiconductor memory device has been proposed. In the NAND flash memory, the sources and drains of a plurality of memory cells arranged side by side are connected in series with one another. The plurality of memory cells connected in series are treated as a unit and connected to a bit line. In the NAND flash memory, the data is written into or read from all or half of the cells arranged in the direction of a row at the same time. In recent years, a multivalued memory that enables a plurality of data items to be stored in a cell of the NAND flash memory has been developed.
This type of nonvolatile semiconductor memory device has a memory element area called a ROM block (ROMBLOCK) in which a recognition code or the like for security is stored. The ROM block, which is selected by a special command, is allocated to a part of the redundant cells for remedying faulty cells in the memory cell array. Consequently, when a part of the redundant cells are at fault, this causes a problem: the ROM block cannot be used.
In addition, since the ROM block uses a part of the redundant cells, it is difficult to set the ROM block in the write inhibit or erase inhibit mode, as the need arises.
The NAND flash memory has a plurality of blocks. The data is erased in blocks. The faulty block which has a faulty cell is replaced with a redundancy block. However, when the number of faulty blocks is larger than that of redundancies, the product is shipped as a partially good product, with the faulty block left. In this case, to recognize the faulty block, data “0” is written in the first several bits of the faulty block. When the faulty block is accessed, data “0” is outputted. Data “0” is not always written into the cells in the faulty block. It might not be written into them. In this case, although most of the memory cells are good, the product must be discarded. As a result, this results in a decrease in the yield.
Accordingly, there have been demands for a semiconductor memory device capable of not only storing security information reliably but also, when a faulty block is present in part of the memory, recognizing the faulty block reliably.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided a semiconductor memory device comprising: a memory cell array with a first and a second storage area, the first storage area having a plurality of memory elements selected by an address signal and the second storage area having a plurality of memory elements selected by a control signal; and a control circuit which has a fuse element and, when the fuse element has been blown, inhibits at least one of writing and erasing from being done on the second storage area.
REFERENCES:
patent: 5363334 (1994-11-01), Alexander et al.
patent: 5590086 (1996-12-01), Park et al.
patent: 5631871 (1997-05-01), Park et al.
Shibata Noboru
Tanaka Tomoharu
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Tran Andrew Q.
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