Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-10-05
2003-04-01
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185280
Reexamination Certificate
active
06542411
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technology effective for application to a system for controlling writing and erasing effected on an electrically programmable erasable nonvolatile memory and a system for controlling a booster circuit. The present invention also relates to, for example, a technology effective for use in a flash memory capable of collectively erasing data in block units, and a microcomputer with the flash memory built therein.
A flash memory makes use of nonvolatile storage or memory elements comprising MOSFETs formed in a two-layer structure having control and floating gates. As a writing system employed in the flash memory, there have heretofore been known, a system using an FN tunnel phenomenon and a system using hot electrons. The system using the FN tunnel phenomenon is a system wherein a voltage is applied between a control gate and a substrate (or well region) or between the control gate and the source or drain to inject an electrical charge into the floating gate or discharge it therefrom by use of the FN tunnel phenomenon, thereby changing a threshold voltage. On the other hand, the system using the hot electrons is a system wherein a current is caused to flow between a source and a drain in a state in which a high voltage is applied to a control gate and hot electrons produced in a channel are injected into a floating gate, thereby changing a threshold voltage.
The FN tunnel-based writing system has an advantage in that since a write current is small, writing is allowed in word-line units like 128 bytes, for example, and hence batch writing can be performed. In the writing system using the hot electrons on the other hand, batch writing in word-line units is difficult because a write current increases, and hence the writing is carried out in units of one byte. Storage or memory elements at the adoption of the FN tunnel-based writing system are difficult in micro-fabrication from relationships with withstand voltages and are not improved in integration density or degree. Therefore, the hot electron-based writing system is advantageous over the FN tunnel-base writing system in terms of an increase in capacity.
Incidentally, even when either of the writing system is adopted, the erasing of data in the flash memory is often carried out in block units, i.e., simultaneously with respect to a plurality of sectors which share the use of a well region and a source line.
SUMMARY OF THE INVENTION
The present inventors have discussed in detail the technology of shortening the time required for writing in the flash memory which has adopted the hot electron-based writing system.
With a view toward performing control on writing and erasing of a flash memory in a microcomputer with the flash memory built-in (hereinafter called a “micon with a built-in flash”), a system has heretofore been adopted wherein a CPU sets write and erase bits of a control register lying within a flash control circuit and starts writing or erasing, and when the CPU manages time according to a program and a suitable time has elapsed, the CPU releases the write and erase bits to thereby complete write and erase operations. In the above-described micon with the built-in flash, which has adopted the FN tunnel-based writing system for performing writing simultaneously in the form of one sector (e.g., 128 bytes) corresponding to word-line units, for example, even the above-described control system whose time management is performed by the CPU, was effective because the time required to apply a write voltage was sufficiently longer than an operating period or cycle of the CPU. Even in the case of a so-called single flash memory built-in packaged with a controller for performing write control or the like on a flash memory, the controller has performed similar time management.
However, in the micon with the built-in flash, which has adopted the hot electron-based writing system, write pulses must be applied to drains of memory cells in the sector being in selection as described above in order bit by bit or in 8-bit units. In this case, the width of each write pulse becomes very short as compared with the FN-tunnel system. Therefore, the CPU is difficult to accurately control such a short time except when the operating frequency of the CPU is sufficiently high. When a margin therefor is sufficiently ensured, a write time required becomes long and a high voltage is applied even to each non-selected memory cell, whereby a phenomenon called “threshold voltage-varying disturb” is apt to occur. On the other hand, a problem arises in that when the margin for the write pulse width is reduced, a write failure occurs and hence the number of times that pulses are applied up to the completion of writing, increases, so that the total time required for the writing becomes long.
Further, a problem arises in that an overhead time attendant on communications between the CPU and each memory is also included in the time required.
In the system wherein the CPU or controller manages the write pulses even in the case of the single flash as well as the micon with the built-in flash, the CPU or the like determines an end time assuming the worst case in regard to the characteristic of each storage element and a source voltage. Therefore, a flash memory good in characteristic will often cause needless latency time.
Further, when it is desired to type diversification of products different in storage capacity of flash memories, products different in operating frequency thereof, products different in source voltage, etc. in the micon with the built-in flash and the single flash, a boosting time for a booster circuit for generating a write voltage used for the flash memory also changes with a change in product. Therefore, the system wherein the write pulses are managed by the CPU or the like as described above, was also accompanied by a problem that it needed to re-design the booster circuit for each type and take measures such as rightsizing for a CPU's program correction and controller's control, and the time required to develop a new product became long.
An object of the present invention is to provide a nonvolatile memory like a flash memory capable of shortening a total write time required, and a semiconductor device such as a microcomputer with the nonvolatile memory built therein.
Another object of the present invention is to make it possible to provide a nonvolatile memory like a flash memory capable of performing writing and erasing in a optimum time without taking measures such as the re-design of a booster circuit, rewriting or updating of a CPU's program, etc. even in the case where internal booster circuits are different in boosting time due to the difference between specifications of storage capacities or the like, and a semiconductor device such as a microcomputer with the nonvolatile memory built therein.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be explained in brief as follows:
A nonvolatile memory like a flash memory having adopted a hot electron-based writing system, or a semiconductor device with the nonvolatile memory built therein is provided with a memory array having a plurality of nonvolatile memory elements which store data according to magnitudes of threshold voltages thereof, a booster circuit which generates a voltage applied to each of the nonvolatile memory elements upon writing or erasing of the data, a boosted voltage detecting circuit which detects the level of the voltage boosted by the booster circuit, a write/erase control circuit which starts the writing or erasing based on the detection of the voltage by the boosted voltage detecting circuit, a write/erase end detecting circuit which detects the completion of the writing or erasing started by the write/erase control circuit, and an end flag indicative of the completion of the writing or
Fujito Masamichi
Kawajiri Yoshiki
Shinagawa Yutaka
Tanaka Toshihiro
Tanikawa Hiroyuki
Lebentritt Michael S.
Miles & Stockbridge P.C.
Phung Anh
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