Integrated circuitry conductive lines

Details Integrated circuitry conductive lines Integrated circuitry conductive lines

1997-04-22

2003-08-26

Williams, Alexander O. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C257S638000, C257S754000, C257S758000, C257S756000, C257S316000, C257S505000, C257S506000, C257S508000, C257S510000, C257S520000, C257S208000, C257S211000

Reexamination Certificate

active

06611059

ABSTRACT:

TECHNICAL FIELD
This invention relates to semiconductor processing methods of forming a series of conductive lines and to integrated circuitry having lo a series of conductive lines.
BACKGROUND OF THE INVENTION
The high speed operation of future higher density integrated circuits will be dictated by interconnect response. Realization of such high speed circuitry is impacted by cross-talk between different adjacent interconnect lines. Cross-talk imposes the biggest constraint on high speed operation when frequencies exceed 500 MHz. Lowering the conductive line resistivity or the dielectric constant of insulators interposed between conductive metal lines is not expected to inherently solve the cross-talk problem. In addition, the gain in system response is only enhanced by a factor of 3, at best, when these changes are ideally integrated into manufacturing processes.
Future circuits will also incorporate higher drive devices. In such situations, as the circuits change state (e.g., from high voltage to low voltage in a CMOS circuit), the interconnect line that carries the signal to the next active device will often be closely spaced to another interconnect line whose driver is not changing state. However given the speed of the voltage change on the first line and the spacing from the second, capacitive coupling will undesirably cause the second line to follow the first momentarily. This situation is made worse when the device driving the second line is small compared to the driver switching the first line. Here, the driver driving the second line does not have enough drive to maintain the output line's desired voltage during the first line's transition from high voltage to low voltage. Therefore, the second line follows the first. This can cause upset in circuits tied to the second line and cause the chip to fail or temporarily operate incorrectly.
One prior art technique to decouple adjacent interconnect lines is to fully enclose lines in a conductive shield, such as a coaxial sheath around a central core interconnect line. Such processing to produce such construction is however complex, and alternate methods and resultant circuitry constructions are desired.


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