Radiation imagery chemistry: process – composition – or product th – Plural exposure steps
Reexamination Certificate
2001-04-02
2003-09-02
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Plural exposure steps
C430S030000, C430S312000, C430S322000
Reexamination Certificate
active
06613500
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to processing a semiconductor substrate. In particular, the present invention relates to reducing post-develop defects present on a photoresist clad wafer.
BACKGROUND ART
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such high device packing densities, smaller and smaller feature sizes are required. Since numerous conductive features are typically present on a semiconductor wafer, the trend toward higher device densities is a notable concern.
The requirement of small features (and close spacing between adjacent features) requires high resolution lithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the photoresist. The photoresist coated substrate is baked to evaporate any solvent in the photoresist composition and to fix the photoresist coating onto the substrate. The baked coated surface of the substrate is next subjected to selective radiation using a mask; that is, a mask is employed to effect an image-wise exposure to actinic radiation. The mask permits radiation to contact certain areas of the photoresist and prevents radiation from contacting other areas of the photoresist. This selective radiation exposure causes a chemical transformation in the exposed areas of the photoresist coated surface. Types of radiation commonly used in microlithographic processes include visible light, ultraviolet (UV) light, deep ultraviolet (DUV) light and electron beam radiant energy. After selective exposure, the photoresist coated substrate is treated with a developer solution to dissolve and remove either the radiation-exposed or the unexposed areas of the photoresist (depending upon whether a positive photoresist or a negative photoresist is utilized) resulting in a patterned or developed photoresist.
Due to the large number of critical masking steps in a modern process flow and the inherent ability to impact pattern fidelity, photolithographic defects are particularly dangerous. The ability to detect and eliminate new defect types becomes increasingly important as integrated circuit device geometries continue to shrink into the deep sub-micron regime. Post-develop residue is a common defect phenomenon particularly in DUV lithography which occurs at a critical mask layer. For example, post-develop defects may occur at an active mask layer on a nitride film and/or at a polysilicon mask on a polysilicon/silicon oxide film or on a silicon nitride BARC (bottom anti-reflective coating) film.
Formation of post-develop or resist residue defects commonly occurs during a pattern image transfer associated with a lithography process. As a result of irradiating a photoresist through a photomask, resist residue or byproducts often form on the photoresist. A developer solution is then deposited over the selectively irradiated photoresist. However, the solubility of the radiation sensitive Photo Acid Generator (PAG) contained in the photoresist can be low. Moreover, it is believed that low solubility rates of the PAG in the developer are exacerbated by the presence of impurities (calcium, sulfur), which cause exposed (open) regions of the resist to be incompletely dissolved in the developer solution within a common process time (typically a 60 to 90 second develop time). As a result, circular defects are generated and remain on the wafer at the completion of the development cycle.
While not wishing to be bound by any theory, it is believed that the solubility rate of the photoresist including the PAG can be enhanced by providing more energy to the photoresist during the inventive lithography process without impacting tiny geometry dimensions. Therefore, as a result of the present invention, resist residues can be substantially, if not completely, dissolved during a standard develop process.
FIGS. 1 and 2
show two common circuit patterns exhibiting this post-develop defect phenomenon. In particular,
FIG. 1
illustrates a plan view of a patterned photoresist clad wafer
10
. The photoresist
12
has an exemplary layout for a memory device patterned thereon comprising a core circuit
14
and a periphery circuit
18
. The circuit patterns
14
and
18
may be formed by a DUV lithography process using a conventional poly gate or circuit mask (not shown). Resist residues (not shown) or resist byproducts of the resist processing are also present on the photoresist before development. After development, post-develop defects
22
undesirably form on the photoresist where they may cause problems. Post-develop defects
22
primarily tend to appear in the open and/or peripheral areas of the wafer
10
. However, it should be understood that post-develop defect density and distribution varies with the particular mask layout employed.
Post-develop defects may also be interspersed in the open areas between circuit patterns of a logic device structure.
FIG. 2
illustrates a plan view of a patterned photoresist clad wafer
26
for such a device. Following development of the photoresist
28
, post-develop defects
34
are primarily detected in the open areas
38
around and/or outside of the circuit patterns
30
. With respect to logic device structures, it should be appreciated that defect distribution is layout sensitive (logic device layout) while defect density varies with the logic device mask layout as well as the resist process employed.
If the resist residue (resist byproducts) contains impurities, such as carbon, calcium (such as in the form of CaF), nitrogen and/or sulfur, the defects become robust enough to withstand decay during a subsequent etch process. Hence, poor fidelity of the desired pattern at that layer results (the defects prevent processing of the underlying layer).
Post-develop defects tend to have a circular appearance and thus are typically referred to as circular, satellite or cluster defects. Due to their subtle physical characteristics and low density, these defects are often dismissed as non-fatal defects. However, they may contribute to yield loss and raise device reliability issues because of the sheer volume (hundreds to thousands) of such defects on the wafer. In addition, despite their subtle physical characteristics, they can undesirably act as a hard mask, resulting in pattern deformation after etch. Thus, pattern deformation poses a substantial yield risk. In light of these problems, there is an unmet need for detecting, reducing and controlling the presence of post-develop defects at critical mask layers.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides a method for improving wafer sort yield and product reliability by reducing post-develop defects at critical mask layers. More specifically, the present invention provides a method for reducing post-develop defects at critical mask layers by exposing a photoresist through a defect trim mask with a high dose of energy. The present invention involves dissolving all or substantially all resist residues in the open regions outside circuit sensitive areas without substantially any impact on critical dimension control and pattern fidelity of the circuit.
One aspect of the present invention relates to a method for reducing resist residue defects involving providing a semiconductor structure having a phot
Erhardt Jeff
Phan Khoi A.
Singh Bhanwar
Subramanian Ramkumar
Templeton Michael K.
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Huff Mark F.
Sagar Kripa
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