System and method for introducing multiple component-type...

Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing

Reexamination Certificate

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C700S121000

Reexamination Certificate

active

06611729

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to yield prediction and, more specifically, to a system and method for introducing multiple component-type factors into an integrated circuit yield prediction.
BACKGROUND OF THE INVENTION
In the realm of semiconductor fabrication, the ability to predict the yield of a semiconductor wafer with respect to the number of integrated circuit chips that will function within their design specifications is of paramount importance. This capability impacts an organization's planning, marketing, design, process development, product engineering, manufacturing and management functions to a great degree. This range of organizational impact motivates semiconductor fabricators to develop tools that may be used to predict the yields of semiconductor wafers. Some of these tools are models, which have their origin in quality assurance programs.
Quality assurance programs that focus on producing a high percentage of acceptable semiconductor devices typically require constant checking for defects. Thus, semiconductor manufacturers have attempted to integrate frequent quality control checks into the fabrication process wherein this process of checking is typically performed in all stages of production. Many types of defects may arise from process contaminants during the manufacturing process. These defects may be classified either as “fatal” or non-critical. Fatal defects are capable of causing a malfunction or failure in the semiconductor device. Non-critical defects do not substantially affect the performance of the semiconductor device.
Fatal defects are highly undesirable, because they often require that the defective semiconductor device be destroyed and another be manufactured in its place, thereby increasing the overall cost of manufacturing the final device. If there are a high number of fatal defects causing the number of functional dies on the semiconductor wafer to be low, it may not be economically viable to further process the wafer into packaged chips. However, non-critical defects typically cause few problems and are therefore of limited concern when fabricating semiconductor devices.
Yield models may be used to predict the number of dies on a semiconductor wafer that will meet their design specifications. Different integrated circuit architectures usually provide different defect densities. This may occur due to either a complexity of the circuit components, the extent of die real estate needed to construct the circuit or factors involving both of these. The capability of current yield models to accurately predict wafer yield is limited when a particular die contains a collection of different circuit architectures. This limitation reduces the value of many current yield prediction estimating techniques.
Accordingly, what is needed in the art is an improved way to incorporate diverse defect characteristics of different circuit architectures in estimating semiconductor wafer yields.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a system for, and method of, introducing multiple component-type factors into a yield prediction regarding a wafer. In one embodiment, the system includes: (1) a first routine that accepts a first factor representing a probability of a first component-type area of an integrated circuit on the wafer being functional and (2) a second routine, associated with the first routine, that accepts a second factor representing a probability of a second component-type area of the integrated circuit being functional.
The present invention therefore introduces the broad concept of taking multiple component-types into account before undergoing a yield prediction with respect to a wafer. The resulting yield prediction becomes substantially more accurate, allowing costs and prices of future integrated circuits to be predicted more precisely. “Component-type” is defined as an architecturally similar portion of circuitry, often, but not always, corresponding to a particular function to be carried out. In examples that follow, component-types include “memory” (such as static random access memory (SRAM) and dynamic access memory (DRAM)), so-called “logic” or “standard circuitry” (the circuitry, such as data processing circuitry, that typically cooperates with memory in a particular class of integrated circuit) and “null circuitry” (blank spaces on a wafer that do not contain active circuitry).
In one embodiment of the present invention, the first factor is based on a defect density of a first component-type and a size of the first component-type area. In a related embodiment, the second factor is based on a defect density of a second component-type and a size of the second component-type area.
In one embodiment of the present invention, the first factor is exponentially related to a defect density of a first component-type. In a related embodiment, the second factor is exponentially related to a defect density of a second component-type.
In one embodiment of the present invention, the first component-type is selected from the group consisting of: (1) a standard component, (2) a memory component and (3) a null component. The present invention is not limited to these particular component-types.
In one embodiment of the present invention, the probability is determined by employing a function selected from the group consisting of: (1) a Poisson function, (2) a Murphy function and (3) a negative binomial function. Those skilled in the pertinent art will understand, however, that other conventional or later-discovered probability functions are within the broad scope of the present invention.
In one embodiment of the present invention, the system further includes a third routine, associated with the first and second routines, that performs the yield prediction employing results of the first and second routines. The present invention is not limited to employing results of the first and second routines.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.


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patent: 5128737 (1992-07-01), van der Have
patent: 5487039 (1996-01-01), Sukegawa
patent: 5539652 (1996-07-01), Tegethoff
patent: 5539752 (1996-07-01), Berezin et al.
patent: 5773315 (1998-06-01), Jarvis
patent: 6214630 (2001-04-01), Hsuan et al.
patent: 6284553 (2001-09-01), Steffan et al.
William Stallings, “Computer Organization and Architecture,” MacMillan Publishing Company, USA, (3rd ed. 1993).

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