Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-09-30
2003-03-18
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000
Reexamination Certificate
active
06535193
ABSTRACT:
FIELD OF THE INVENTION AND RELATED ART
The present invention relates to a display apparatus including a display device, particularly a display apparatus improved in drive control method of a display device having scanning electrodes and data electrodes arranged in a matrix form.
In recent years, display devices using liquid crystals (e.g., an STN (super twisted nematic) liquid crystal, an FLC (ferroelectric liquid crystal) and an AFLC (anti-ferroelectric liquid crystal)) of, e.g., a single matrix-type and an active matrix-type (using TFTs (thin film transistors) etc.) have been extensively developed in view of a large picture area (size) and a large display capacity (the number of pixels). Specifically, e.g., large-sized display devices (panels) having a diagonal length of 10-14 in. for notebook-type PCs (personal computers) and 13 in. to above 20 in. for monitors of desktop-type PCs and high-definition (resolution) display devices (panels) of XGA mode (1024×768 pixels), SXGA mode (1280×1024 pixels) and UXGA mode (1600×1280 pixels) have been announced.
These display panels have such an electrode structure that scanning electrodes and data electrodes are arranged in a matrix form and generally driven by successively scanning the scanning electrodes in a line-sequential scheme while inputting picture image information (display data) into the data electrodes.
FIG. 4
is a block diagram showing an embodiment of a display apparatus using such a conventional display panel (device).
Referring to
FIG. 4
, the display apparatus includes a liquid crystal panel
401
having scanning electrodes
1
and data electrodes
2
arranged in a matrix form, a scanning electrode drive circuit
403
for applying scanning signals to the scanning electrodes
1
, a data electrode drive circuit
402
for applying data signals to the data electrodes
2
, and a panel control circuit
404
for inputting a scanning electrode drive timing signal into the scanning electrode drive circuit
403
and inputting a data electrode drive timing signal into the data electrode drive circuit
402
.
Picture image display in the display apparatus is performed based on (picture) image data transmitted from a display data generating unit
405
.
Heretofore, the data electrode drive circuit (generally called a segment or source driver)
402
and the scanning electrode drive circuit (generally called a common or gate driver)
403
have been designed according to the same IC (integrated circuit) process rule and have possessed an identical withstand voltage.
However, in more recent years, in order to meet, e.g., a cost reduction of the entire drive circuits and an increase in transfer clock frequency due to an increased display capacity for providing a high definition or resolution, the data electrode drive circuit has been prepared by a minute production process and/or by using driver ICs of lower withstand voltages. As a result, the data electrode drive circuit has included driver ICs having a withstand voltage different from a withstand voltage of driver ICs for the scanning electrode drive circuit in many cases.
In an ordinary simple matrix-type display apparatus using a STN (TN) liquid crystal, the data electrode drive circuit generally has a structure (block diagram) as shown in FIG.
5
and the scanning electrode drive circuit generally has a structure as shown in FIG.
6
. For another simple matrix-type display apparatus using an FLC possessing a memory characteristic, the data electrode drive circuit and the scanning electrode drive circuit generally have structures partially different from those (
FIGS. 5 and 6
) for the display apparatus using the STN (TN) liquid crystal due to different drive waveforms therebetween. However, problematic portions considered in the present invention are substantially common to the STN (TN)-type display apparatus and the FLC-type display apparatus.
As shown in
FIGS. 5 and 6
, the data electrode drive timing signal comprising a latch signal (LP) for display data and an AC (alternating current)-providing signal (M) for a liquid crystal drive waveform (a timing signal for inverting a polarity of a liquid crystal drive waveform) is inputted into the data electrode drive circuit and the scanning electrode drive timing signal comprises shift clock signal (SCL) and an AC-providing (or polarity-inversion) signal (M) is inputted to the scanning electrode drive circuit. These signals are generally applied in accordance with a time chart as shown in FIG.
9
.
Herein, the drive timing signal means a signal for determining a time (or timing) for switching a liquid crystal drive waveform.
In the case where a matrix-type display panel is driven by using these (scanning and data electrode) drive circuits, as shown in
FIG. 4
, the panel control circuit
404
inputs an identical signal providing a latch signal (LP) for the data electrode drive circuit
402
and a shift clock signal (SCL) for the scanning electrode drive circuit
403
and an identical signal providing an AC-providing signal (M) for the data electrode drive circuit
402
and an AC-providing providing signal (M) for the scanning electrode drive circuit
403
, respectively.
In such a case, if parameters regarding an operating speed, such as a withstand voltage of an output stage and a circuit structure of the data electrode drive circuit
402
, are identical to those of the scanning electrode drive circuit
403
, an outputted data electrode drive waveform and an outputted scanning electrode drive waveform are switched at the same time with an identical delay time based on the above-mentioned drive timing signals transmitted from the panel control circuit
404
as shown in FIG.
7
.
Referring to
FIG. 7
, a delay time td
1
is a time from an input of an AC-providing signal (M) to a switching (output) of an actually outputted drive waveform and a delay time td
2
is a time from an input of a latch signal (LP) or a shift cock signal (SCL).
A correlation between the delay times td
1
and td
2
determined based on the signals (M) (LP) and (SCL) is not restricted to that shown in FIG.
7
. The delay times td
1
and td
2
are independent of each other.
Herein, each of the delay times (e.g., td
1
and td
2
) is specifically determined as an interval (duration) of time from a time at which an amplitude of an inputted waveform is changed by 90% thereof (i.e., 100% to 10% for highest level or 0% to 90% for lowest level) to a time at which an amplitude of an outputted waveform is changed by 10% thereof (i.e., 100% to 90% for highest level or 0% to 10% for lowest level) in view of a recognizable level of respective switched waveforms.
With respect to the respective drive timing signals, it is important for times (or timings) of switching of outputted scanning and data electrodes drive waveforms to coincide with each other.
However, e.g., in the case where a withstand voltage of an output stage for a data electrode drive circuit is lower than that of an output stage for a scanning electrode drive circuit while adopting a common connection scheme for drive timing signals as shown in
FIG. 4
, driver ICs possessing a lower withstand voltage generally provide a quicker (higher) operating speed due to a structure thereof. As a result, as shown in
FIG. 8
, a data electrode drive waveform outputted from the data electrode drive circuit is switched earlier than a scanning electrode drive waveform outputted from the scanning electrode drive circuit.
Specifically, referring to
FIG. 8
, delay times for the AC-providing signal (M) td
1
s (data electrode side) and td
1
c (scanning electrode side) hold the relationship of: td
1
s<td
1
c. Similarly, delay times for the latch signal (LP)/shift clock signal (SCL) td
2
s (data electrode side) and td
2
c (scanning electrode side) hold the relationship of: td
2
s<td
2
c. Accordingly, when the matrix-type display panel is driven, the outputted scanning electrode drive waveform from the scanning electrode drive circuit and the outputted data electrode drive waveform from the data electrode drive
Mizutome Atsushi
Ohno Tomoyuki
Anyaso Uchendu O.
Saras Steven
LandOfFree
Display apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Display apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Display apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3074175