Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-03-29
2003-01-07
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185200, C365S185210, C365S185220
Reexamination Certificate
active
06504762
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semi-conductor electrically programmable read only memories (Eprom) and electrically erasable programmable read only memories (EEprom), and specifically to semiconductor structures of such memories, processes of making them, and techniques for using them.
An electrically programmable read only memory (Eprom) utilizes a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over but insulated from a channel region in a semi-conductor substrate, between source and drain regions. A control gate is then provided over the floating gate, but also insulated therefrom. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions is controlled by the level of charge on the floating gate. A transistor is programmed to one of two states by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate.
The memory cell transistor's state is read by placing an operating voltage across its source and drain and on its control gate, and then detecting the level of current flowing between the source and drain as to whether the device is programmed to be “on” or “off” at the control gate voltage selected. A specific, single cell in a two-dimensional array of Eprom cells is addressed for reading by application of a source-drain voltage to source and drain lines in a column containing the cell being addressed, and application of a control gate voltage to the control gates in a row containing the cell being addressed.
This type of Eprom transistor is usually implemented in one of two basic configurations. One is where the floating gate extends substantially entirely over the transistor's channel region between its source and drain. Another type, preferred in many applications, is where the floating gate extends from the drain region only part of the way across the channel. The control gate then extends completely across the channel, over the floating gate and then across the remaining portion of the channel not occupied by the floating gate. The control gate is separated from that remaining channel portion by a thin gate oxide. This second type is termed a “split-channel” Eprom transistor. This results in a transistor structure that operates as two transistors in series, one having a varying threshold in response to the charge level on the floating gate, and another that is unaffected by the floating gate charge but rather which operates in response to the voltage on the control gate as in any normal field effect transistor.
Early Eprom devices were erasable by exposure to ultraviolet light. More recently, the transistor cells have been made to be electrically erasable, and thus termed electrically erasable and programmable read only memory (EEprom). One way in which the cell is erased electrically is by transfer of charge from the floating gate to the transistor drain through a very thin tunnel dielectric. This is accomplished by application of appropriate voltages to the transistor's source, drain and control gate. Other EEprom memory cells are provided with a separate, third gate for accomplishing the erasing. An erase gate passes through each memory cell transistor closely adjacent to a surface of the floating gate but insulated therefrom by a thin tunnel dielectric. Charge is then removed from the floating gate of a cell to the erase gate, when appropriate voltages are applied to all the transistor elements. An array of EEprom cells are generally referred to as a Flash EEprom array because an entire array of cells, or significant group of cells, is erased simultaneously (i.e., in a flash).
EEprom's have been found to have a limited effective life. The number of cycles of programming and erasing that such a device can endure before becoming degraded is finite. After a number of such cycles in excess of 10,000, depending upon its specific structure, its programmability can be reduced. Often, by the time the device has been put through such a cycle for over 100,000 times, it can no longer be programmed or erased properly. This is believed to be the result of electrons being trapped in the dielectric each time charge is transferred to or away from the floating gate by programming or erasing, respectively.
It is the primary object of the present invention to provide Eprom and EEprom cell and array structures and processes for making them that result in cells of reduced size so their density on a semiconductor chip can be increased. It is also an object of the invention that the structures be highly manufacturable, reliable, scalable, repeatable and producible with a very high yield.
It is yet another object of the present invention to provide EEprom semiconductor chips that are useful for solid state memory to replace magnetic disk storage devices.
Another object of the present invention is to provide a technique for increasing the amount of information that can be stored in a given size Eprom or EEprom array.
Further, it is an object of the present invention to provide a technique for increasing the number of program/read cycles that an EEprom can endure.
SUMMARY OF THE INVENTION
These and additional objects are accomplished by the various aspects of the present invention, either alone or in combination, the primary aspects being briefly summarized as below:
1. The problems associated with prior art split channel Eprom and split channel Flash EEprom devices are overcome by providing a split channel memory cell constructed in one of the following ways:
(A) In one embodiment, one edge of the floating gate is self aligned to and overlaps the edge of the drain diffusion and the second edge of the floating gate is self aligned to but is spaced apart from the edge of the source diffusion. A sidewall spacer formed along the second edge of the floating gate facing the source side is used to define the degree of spacing between the two edges. Self alignment of both source and drain to the edges of the floating gate results in a split channel Eprom device having accurate control of the three most critical device parameters: Channel segment lengths L
1
and L
2
controllable by floating gate and control gate, respectively, and the extent of overlap between the floating gate and the drain diffusion. All three parameters are insensitive to mask misalignment and can be made reproducibly very small in scaled-down devices.
(B) In a second embodiment of the split channel Eprom a heavily doped portion of the channel adjacent to the drain diffusion is formed by a novel, well-controlled technique. The length Lp and doping concentration of this channel portion become the dominant parameters for programming and reading, thereby permitting the formation of a split channel structure which is relatively insensitive to misalignments between the floating gate and the source/drain regions.
2. A separate erase gate is provided to transform a Eprom device into a Flash EEprom device. The area of overlap between the floating gate and the erase gate is insensitive to mask misalignment and can therefore be made reproducibly very small.
3. In some embodiments of this invention, the erase gate is also used as a field plate to provide very compact electric isolation between adjacent cells in a memory array.
4. A new erase mechanism is provided which employs tailoring of the edges of a very thin floating gate so as to enhance their effectiveness as electron injectors.
5. A novel intelligent programming and sensing technique is provided which permits the practical implementation of multiple state storage wherein each Eprom or flash EEprom cell stores more than one bit per cell.
6. A novel intelligent erase algorithm is provided which results in a significant reduction in the electrical stress experienced by the
Nguyen Viet Q.
SanDisk Corporation
Skjerven Morrill LLP
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