Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-07-14
2003-05-13
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S541000, C327S333000
Reexamination Certificate
active
06563372
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electrical circuits and, more particularly, to a device for the control of a translator-type high voltage switch.
BACKGROUND OF THE INVENTION
Electrically programmable non-volatile memories found in integrated circuits are programmed using a voltage with a level higher than that of the logic supply voltage Vcc for the integrated circuit. The value of this high programming voltage depends upon the integrated circuit technology being used.
To apply the high programming voltage to an integrated circuit element (e.g., a row of memories), it is common practice to use a high voltage selector switch, also called a level translator. At its inputs, the selector switch receives a logic control signal and a high input voltage. Depending on the logic level (i.e., Vcc or zero) of the logic control signal (which, in the case of a memory, will come from a write control signal), either ground or the high input voltage level is provided at an output of the selector switch. These selector switches are well known to those skilled in the art.
In particular, CMOS selector switches typically have two arms, where each arm has two transistors connected in series between the high input voltage and ground. The bottom transistors are N type transistors and have their respective sources connected to ground. The bottom transistors are also called selector switch transistors because one receives the selection switching signal and the other receives the reverse selection switching signal. The selection switching signals are logic signals of zero or Vcc. The toP type transistors are P type transistors and have their sources connected to a node receiving the high input voltage. Each toP type transistor has its gate connected to the drain of the upper transistor of the other arm. The bottom transistors are also called load transistors.
Depending upon the levels of the selection switching signals, one selector switch N type transistor is always off and the selector switch N type transistor of the other arm will always be on. The N type transistor that is on draws its drain toward zero volts (the potential of its source), and the P type transistor of the other arm, which has its gate connected to this drain, turns on. The P type transistor therefore takes its own drain to the voltage of its source, that is, to the high input voltage level. Thus, at each connection node of the drains of the N and P type transistors of one arm, ground or the high input voltage level will be present.
These selector switches usually have an intermediate stage between the stage of the top transistors and the stage of the bottom transistors. The intermediate stage includes one or more cascoded stages and enables the internal nodes of the selector switch to be limited to intermediate voltage levels so that no transistor of the selector switch experiences any excessively high voltage at its terminals.
In certain circuits of the prior art, all the MOS transistors (N or P type) of the cascoded stage are biased at their gate by the logic supply voltage Vcc. This bias limits the range of operation of the selector switch. Indeed, the switching over of the selector switch to obtain the high input voltage level at its output can be done only when the level of the input is sufficiently high, which in practice is higher than the logic supply voltage Vcc.
A disadvantage of such circuits is that with thin oxide MOS technologies, the switching operations of the selector switch under high voltage may have harmful transient effects on the MOS transistors. Furthermore, with this kind of biasing of the gates of the cascoded transistors at the logic supply voltage, there is a voltage dependent on the high input voltage at the drains and sources of the cascoded transistors but no link therebetween. This may give rise to additional stresses if the difference between these two voltages becomes to great.
For these reasons, the gates of these cascoded transistors are preferably biased at a reference voltage obtained from the high input voltage. Thus, it is possible to control the voltage difference between the reference voltage and the other high input voltage since the former depends on the latter, thus providing for better protection. In the case of a cascoded stage with N and P type MOS transistors, the gates of the N type transistors of the cascoded stage are usually biased at a reference voltage Vref
n
that is higher than a reference voltage Vref
p
which biases the gate of the P type transistors of the cascoded stage. This makes it possible to bring down the lower switch-over limit of the selector switch.
An exemplary cascoded stage selector switch of this type is shown in FIG.
1
. In this illustration, the upper stage comprises a P type MOS transistor M
1
in the first arm and a P type MOS transistor M
2
in the second arm. These transistors receive the high input voltage Ehv at their respective sources. The bottom stage comprises a N type MOS transistor M
3
in the first arm and a N type MOS transistor M
4
in the second arm. These transistors have their respective sources connected to the ground Gnd.
The cascoded stage comprises four MOS transistors, two P type MOS transistors M
5
and M
6
, one in each arm and beneath each toP type transistor, and two N type MOS transistors M
7
and M
8
, one in each arm and above each bottom transistor. The P type MOS transistors M
5
and M
6
receive the reference voltage Vref
p
at their respective gates. The N type MOS transistors M
7
and M
8
receive the reference voltage Vref
n
at their respective gates.
The output Vout of the selector switch is taken between the N and P type cascoded transistors of one arm, for example, at the drains of the transistors M
6
and M
8
. The gate of the bottom transistor M
3
of the first arm of the selector switch receives a selection switching logic signal reference IN, and the gate of the bottom transistor M
4
of the second arm of the selector switch receives the reverse signal referenced/IN.
The circuit REF generates the reference voltages Vref
n
and Vref
p
and it includes three MOS transistors M
9
, M
10
and M
11
series-connected between the high voltage Vpp and ground. The transistors M
9
, M
10
and M
11
(illustratively shown as P type transistors) act as resistors because each has its gate connected to its drain. The reference voltages Vref
n
and Vref
p
are obtained by taking the voltage on either side of the med-point transistor M
10
.
The role of the cascoded stage is to limit the voltages experienced by the transistors to intermediate levels. Each P type cascoded transistor is biased so that it always remains on. Thus, the source of each of these transistors, and hence the drain of the P type load transistor with which it is connected, cannot go below Vref
p
−Vt
p
, where Vt
p
is the threshold voltage of the P Hype cascoded transistor. Similarly, each N type cascoded transistor is biased so that it always remains on. Thus, its source, and therefore the drain of the selector switch N type transistor with which At is connected, cannot rise above Vref
n
−Vt
n
, where Vt
n
is the threshold voltage of the N type cascaded transistor.
Turning now to
FIG. 2
, an example is presented in which the high input voltage Ehv of the selector switch takes the form of a pulse with a voltage build-up ramp as shown in the curve
1
. The high input voltage Ehv increases linearly from zero to its rated value Vpp (the slope of the increase may be linear, logarithmic, exponential, etc.). The two curves
2
and
3
respectively represent the progress of the reference voltages Vref
n
, Vref
p
.
The curves
2
and
3
show that the reference voltages Vref
n
, Vref
p
follow the voltage build up of the high input voltage Ehv. They also show that the differences between each of these reference voltages and the level of the high input voltage Ehv at the beginning of the ramp (i.e., in the low voltage values of the input Ehv) do not allow the different transistors of the cascoded stage to be conductive. In these low
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Cunningham Terry D.
Jorgenson Lisa K.
Nguyen Long
STMicroelectronics SA
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