Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-08-10
2003-09-02
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S506000, C257S758000
Reexamination Certificate
active
06614092
ABSTRACT:
TECHNICAL FIELD
This invention relates to microelectronic device packages having heat and/or current conducting structures, and methods for manufacturing and processing such packages.
BACKGROUND OF THE INVENTION
Packaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic substrate die encased in a plastic, ceramic, or metal protective covering. The die includes functional devices or features, such as memory cells, processor circuits, and interconnecting wiring. The die also typically includes bond pads electrically coupled to the functional devices. The bond pads can be coupled to pins or other types of terminals that extend outside the protective covering for connecting to busses, circuits and/or other microelectronic assemblies.
As the size of microelectronic device packages decreases to allow the packages to fit into more compact electronic products (such as mobile phones and laptop computers), the distances between adjacent functional devices and between adjacent interconnecting wires decreases. As these distances decrease, the likelihood for capacitive coupling between adjacent structures increases, which can impair or reduce the maximum performance of the packaged microelectronic device.
One approach to decreasing the capacitance between neighboring wires within the die is to reduce the dielectric constant of the solid material between the wires. For example, polyimides (having a dielectric constant of 3.5) have been used to replace silicon dioxide (having a dielectric constant of 4). A more substantial reduction in the dielectric constant is obtained by replacing the solid insulating material typically positioned between layers of the wiring with a gas, such as air. For example, U.S. Pat. No. 5,891,797 to Farrar and U.S. Pat. No. 5,324,683 to Fitch et al. disclose a process for building successive layers of wiring on a semiconductor substrate by temporarily supporting the wires with sacrificial filler material, and then removing the filler material from around the wires by etching or a plasma process to form suspended “air bridges” that conduct electrical signals from one part of the device package to another. The wires can be formed in the filler material using a dual damascene process, such as is disclosed in U.S. Pat. No. 4,962,058 to Cronin et al. The support material can include a resist material, as disclosed in U.S. Pat. No. 5,593,926 to Fujihiri, that can be removed by etching processes (such as the processes disclosed in U.S. Pat. No. 4,561,173 to Te Velde) or evaporative processes (such as the processes disclosed in U.S. Pat. No. 5,408,742 to Zaidel et al.). U.S. Pat. Nos. 5,891,797; 5,324,683; 4,962,058; 5,593,926; 4,561,173; and 5,408,742 are herein incorporated in their entirety by reference.
It can be shown that the maximum unsupported link of an air bridge in an integrated circuit is governed by the following equation:
L
=
32
E
δ
h
2
/
5
p
4
or
≈
1.6
(
E
δ
/
p
)
1
/
4
h
1
/
2
where
L=the unsupported bridge length
E=the modular elasticity of the bridge material
&dgr;=the maximum allowable deflection of the bridge
&rgr;=the density of the bridge material
h=the vertical thickness of the bridge
As microelectronic devices become smaller, the thicknesses of the bridges and the distances between adjacent bridges also become smaller. To prevent the bridges from sagging into each other, the maximum unsupported length of each bridge decreases. For example, if the bridge is made of an aluminum copper silicon alloy (which has a module of elasticity of 71 GPa and a density of 2.79 Mg/m
3
), has a maximum allowable deflection of 5,000 angstroms (including a safety factor), and a thickness of 10,000 angstroms, the maximum unsupported bridge length is approximately 1.6 millimeters. If the maximum allowable deflection is decreased to 2,500 angstroms, and the bridge thickness is reduced to 5,000 angstroms, the maximum unsupported bridge length is approximately 1 millimeter. If the maximum allowable deflection is further decreased to 1,500 angstroms, the maximum allowable unsupported length is approximately 0.6 millimeters. Because current chips typically measure over 1 centimeter along an edge, it becomes increasingly difficult to reduce the thickness of the bridges and the spacing between bridges without supporting the bridges at such frequent intervals that the benefits of unsupported bridge segments (e.g., the reduced dielectric constant of the material adjacent to the bridge) are lost.
Furthermore, as the bridge thickness (and therefore the cross-section of the conductive line forming the bridge) decreases, the resistivity of the wire forming the bridge increases. One approach to addressing this drawback is to reduce the bulk resistivity of the wire, for example, by replacing aluminum alloy wires with copper wires. However, copper has a significantly greater density than aluminum and aluminum alloys, and therefore has only 85% of the unsupported bridge length of an aluminum or aluminum alloy conductor.
Another problem with conventional air bridge designs is that the air adjacent to the wires typically has a lower thermal conductivity than the solid material it replaced. Accordingly, it can be more difficult to transfer heat from the packaged microelectronic device. As a result, the microelectronic device may be more likely to overheat, which can reduce the life expectancy and/or performance level of the device.
Still another problem with conventional air bridge designs is that several process steps are typically required to first form each layer of wiring in the microelectronic device, and then several additional process steps are required to package the device. Accordingly, the overall process of wiring and packaging the device can be expensive and susceptible to process variables and errors.
SUMMARY
The present invention is directed toward microelectronic device packages and methods for forming such packages. A method in accordance with one aspect of the invention includes forming microelectronic device features at least proximate to a surface of a microelectronic substrate, simultaneously forming an external wall portion of the package and a conductive link coupled to at least one of the microelectronic device features, and removing a sacrificial material adjacent to the conductive link to suspend at least a portion of the conductive link between two points. The sacrificial material can include first components and second components arranged in layers to include etch stop layers of the second component disposed between layers of the first component. The method can further include selecting a material for the external wall portion to be the same as the material for the conductive link.
In one aspect of the invention, the package can be inverted before the sacrificial material is removed and solder balls can be coupled to a portion of the conductive link while the microelectronic substrate is in an inverted position. In still another aspect of the invention, the method can include forming a self-supporting internal heat transfer structure within the internal wall of the package, with at least a portion of the heat transfer structure being spaced apart from the microelectronic substrate and the external wall.
The invention is also directed toward a microelectronic device package. In one embodiment, the package can include a microelectronic substrate having first and second microelectronic device features, a conductive link that includes a conductive material extending between the first and second microelectronic device features, and an external cover attached to the substrate and at least partially enclosing the first and second microelectronic device features and the conductive link. In a further aspect of the invention, the external cover can have a composition substantially identical to a composition of the conductive link. The package can further in
Eldridge Jerome M.
Farrar Paul A.
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