Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-10-29
2003-03-25
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185050
Reexamination Certificate
active
06538925
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dual bit nonvolatile programmable read/write memory, a method of manufacturing the same, and a method of driving the same.
2. Description of the Prior Art
In the flash memory, the limit of miniaturization is decided by limits in the reduction in the voltages, the cell area, and the electrostatic capacity scaling. In contrast, the realization of the multivalue operation per one element is expected as the element technology to meet the trend of cost reduction.
Also, there is the memory like the mask ROM, which does not need the reprogramming, among the nonvolatile memories and it is desired to supply the product at a low price. In this case, the realization of the multivalue operation per one element is also watched with interest as the element technology to meet the lower cost.
Under such circumstances, the structure of the nonvolatile memory that makes it possible to realize the multivalue operation per one element is disclosed in the U.S. Patent (U.S. Pat. No. 6,011,725).
According to this Patent, the localization of the trapped charge by the MONOS (Metal Oxide Nitride Oxide Semiconductor) structure is utilized to obtain the 2-bit 4-value states. This system is the unique system that utilizes the event that the threshold value of the device can be decided by the fixed charges located locally near the source region and also the source region and the drain region are exchanged in operation, so that 2-bit (i.e., 4-value states) data can be generated by one transistor.
In FIG.
1
A and
FIG. 1B
of this application, the similar element structure to that of the above U.S. Patent is shown. More particularly, the source/drain regions
6
a,
6
b
serving as the source or the drain are formed at a distance on the surface of the one conductivity type semiconductor substrate
1
, and the ONO (Oxide Nitride Oxide) structure in which the nitride film
3
is sandwiched by oxide films
2
,
4
is formed on the channel region between them, and the control gate
5
is formed on the ONO structure. The overall stacked structure constitutes the MONOS structure.
In the programming of data, the avalanche breakdown is caused in the pn junction, that consists of the source/drain region
6
a
or
6
b
and the semiconductor substrate
1
, by applying the program voltage to the source/drain region
6
a
or
6
b
to generate hot electrons. The electrons are injected into the ONO structure near the pn junction, and then trapped by the electron trap in the nitride film
3
. At this time, normally the trapped electrons are located locally in the nitride film
3
near the pn junction.
FIG. 1B
shows the state that the accumulated charges (trapped electrons)
7
a
and
7
b
are located locally in vicinity of the source/drain regions
6
a
and
6
b
respectively when the program voltage (Vpp) is applied separately to the source/drain regions
6
a
and
6
b
respectively. This state shows one state of the 2-bit 4-value states.
In the reading of this data, the current in one direction is detected while using the source/drain region
6
a
as the source and the source/drain region
6
b
as the drain, and then conversely the current in the opposite direction is detected while using the source/drain region
6
b
as the source and the source/drain region
6
a
as the drain. In both cases, since the accumulated charges
7
a
or
7
b
exist on the source side and thus the electric field to turn off the channel is generated, the detected current is small to indicate the “OFF” state.
However, problems described in the following still remain in the above nonvolatile memory.
(i) Programming Control
In the programming, as described above, normally the trapped electrons are located locally near the pn junction. However, there is the possibility that the trapped electron distribution in the nitride film is expanded by the excessive programming. In this case, since asymmetry of the operation is lost because the localization of the trapped electrons cannot be implemented, it is impossible to execute the dual bit operation. In order to prevent such excessive programming, the precise control of the programming time is needed.
Also, even if the precise control of the programming time can be carried out, the channel length must be set long to some extent in view of the expansion of the trapped electron distribution in the nitride film to locate locally the charges on both sides of the nitride film at the same time. Therefore, it may be concluded that the structure in the prior art is not suitable for the higher density achieved by the miniaturization.
(ii) Variation in the Threshold Value
Since the avalanche breakdown is caused locally, it is difficult to localize the fixed charged uniformly over the overall area along the channel width direction shown in FIG.
1
A.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device which has high reliability and makes it possible to achieve miniaturization and a higher density, and each element of which is operated at multi-values.
It is another object of the present invention to provide a semiconductor memory device capable of achieving lower voltages in a programming voltage and much more expanding a current window defined later.
It is still another object of the present invention to provide a method of manufacturing the above semiconductor memory device.
It is yet still another object of the present invention to provide a method of driving the above semiconductor memory device.
The gist of the inventions set forth in claims will be explained hereunder. In this case, some portions will be explained with reference to the drawings. This intends to explain contents of the invention comprehensively, but this does not intend to limit the scope of the invention.
A semiconductor memory device set forth in claim 1 of the present invention containing a semiconductor memory element, the element comprises a one conductivity type semiconductor substrate in which convex portions having a pair of opposing side surfaces is provided, a pair of opposite conductivity type source/drain regions formed on a surface of the semiconductor substrate on both sides of the convex portion, a first insulating film for covering upper surface of the convex portion, second insulating films for covering the side surfaces of the convex portion and the source/drain regions, a pair of floating gates provided on the sides surfaces of the convex portions to oppose to the side surfaces and the source/drain regions via the second insulating film respectively, third insulating films formed on the floating gates, and control gate opposing to the upper surface of the convex portion via the first insulating film and opposing to the floating gates via the third insulating films respectively.
In this case, as set forth in claim
2
, a region neighboring to the side surfaces and upper surface of the convex portion put between a pair of the source/drain regions acts as a channel region, and a pair of floating gates act as charge accumulating regions for accumulating charges.
In the present invention, two bits are formed per one element by a pair of the floating gates, and 4-value states can be formed by possible combinations of the charge accumulation or no charge accumulation into the one floating gate and the charge accumulation or no charge accumulation into the other floating gate.
Also, since the floating gates are provided on both side surfaces of the convex portion formed on the surface of the semiconductor substrate and also side surfaces of the convex portion are utilized as a channel respectively, a element forming area can be reduced. Also, since the source/drain regions are provided under the floating gates, the higher density of the semiconductor memory device can be achieved.
In the programming, hot carriers (high energy carriers) generated by the electric field directed from the source to the drain are employed as the injection charge. At this time, the energy required for the hot car
Innotech Corporation
Lorusso & Loud
Tran M.
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