Evaluation of conduction at precharged node

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C327S089000, C327S055000

Reexamination Certificate

active

06590428

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is concerned with determining whether a node which has been charged to a given potential remains at that potential or whether the node is being discharged, and thus exhibits a falling potential.
2. Description of the Related Art
There are a number of applications in which a node is charged or precharged by connection to a potential, typically a power supply potential, and a determination is needed as to whether any path exists that is operative to discharge the node once the connection to the potential is removed. In many situations, a circuit has a first logic value when the node remains isolated and a second logic value when a discharge path exists. Typical applications include so-called “precharge-evaluate logic”.
Conventional circuits may give rise to a tentative result that may or may not be correct. For example, if a node is falling slowly in potential from its precharged level, and the node potential is being fed as an input to an inverter, the potential fall may need to be quite a substantial fraction of the precharge potential before the inverter is able to respond to it. Hence for a relatively long period of time—for a slow potential variation—the inverter output remains at its original precharge value and only after its input potential has fallen sufficiently will the output change.
During that time conventional circuits consume power. The tentative result also makes such circuits unsuitable for applications where the output is used asynchronously to enable or otherwise control a later process. To do this, the “disabled state must have an output the same as detecting “discharge” in the active state.
It is possible to avoid effects due to the tentative result either by using a timing circuit to mask the output from later circuitry until the output is known to have a valid result, or by using a clocked comparator with a pseudo-differential reference voltage. The latter is advantageous because it is faster, and so it draws power for a shorter time than does the conventional circuit. However it is also disadvantageous because it needs a reference voltage to be created. A reference circuit is likely to create a quiescent power drain, and also consumes chip area and components.
It is an object of the present invention to at least partly mitigate difficulties of the prior art.
BRIEF SUMMARY OF THE INVENTION
According to one aspect the invention provides a method of determining whether the potential on a node remains constant, the method comprising: providing a differential comparator having a first input connected to said node, a second input connected to a constant potential and an output, wherein said first and second inputs become active at respectively lower and higher potentials, the comparator having a first enabled state in which said output represents the difference between the first and second input potentials and a second disabled state, wherein the comparator has no path for dc currents in said enabled and disabled states; connecting the node to said constant potential whereby said node is precharged, while maintaining the disabled state; disconnecting the node from the precharge potential; and after a time delay, causing said comparator to switch to the enabled state, whereby said output indicates whether the node potential remains constant.
According to a second aspect of the invention there is provided a circuit responsive to deviation of a node from a precharge potential after a precharge supply is disconnected from said node, the circuit comprising: a dynamic comparator having first and second first conductivity differentially connected transistors, the first transistor having a gate connected to the said node and the second having a gate connected to the precharge potential, and wherein the first transistor has a lower threshold voltage than the second; the first and second transistors second and third electrodes, a load circuit being connected between the second electrodes and a positive supply node, the load circuit comprising a pair of cross-coupled second conductivity load transistors, said second conductivity being complementary to the first conductivity; the third electrodes of the first and second transistors being connected to a reference potential via a current source transistor of the first conductivity type.
A preferred but exemplary embodiment of the invention will now be described with reference to the accompanying drawings.


REFERENCES:
patent: 4611130 (1986-09-01), Swanson
patent: 5936432 (1999-08-01), Oh et al.
patent: 6147514 (2000-11-01), Shiratake
patent: 6292030 (2001-09-01), Shih
Huang, H-Y. et al., “Unbalanced Current Latch Sense Amplifier for Low-Power High-Speed PLD's,”in Proceedings of the IEEE International Symposium on Circuits and Systems, New York, May 12, 1996, pp. 193-196.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Evaluation of conduction at precharged node does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Evaluation of conduction at precharged node, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Evaluation of conduction at precharged node will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3070721

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.