Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-05-03
2003-09-16
Tran, M. (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S203000
Reexamination Certificate
active
06621758
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to Read Only Memory (ROM) devices for use with microcontroller-based products.
BACKGROUND OF THE INVENTION
The demand for higher performance, microcontroller-based products for use in communication and processing applications continues to increase rapidly. As a result, microcontroller-based product manufacturers are requiring the components and devices within these products to be continually improved to meet the design requirements of a myriad of emerging audio, video and industrial control applications.
These microcontroller-based products use various types of processors. Typical processors may include general purpose microprocessors for controlling the logic of various digital devices, such as clock radios, microwave ovens, digital video recorders and the like. Other microcontroller-based products may use special purpose microprocessors, such as math coprocessors for mathematical computations, or digital signal processors used in manipulating various types of information, including sound, imaging, video and industrial control information.
A typical microprocessor may include a central processing unit (CPU) core for facilitating processing functions, and a bus interface for communication with the various memory and peripheral devices.
For the storage of data, the microprocessor can include various types of memory. For example, the CPU for the microcontroller may include Random Access Memory (RAM) as well as Read-Only Memory (ROM), i.e., programmed memory. In addition, the microcontroller can also include flash memory which can be erased and preprogrammed in blocks instead of being programmed one byte at a time.
Beneficially, ROM is a non-volatile memory and, theoretically, can maintain the data it stores indefinitely without power. Inside ROM memory, data may be stored in memory cells and blocks of memory cells may be stored in separate memory banks. As discussed more fully below, by organizing the memory cells into a bank, bit line loading is reduced and ROM accessing speed is improved.
The basic component of a memory cell is a transistor and hence will be referred to as a memory cell transistor. In a typical ROM structure, the memory cell transistor is capable of generating a binary digit. A binary digit is either a logic ‘1’ (high voltage level) or a logic ‘0’ (low voltage level). In a typical memory cell arrangement, two sets of 8 transistors are grouped in each row to create two ‘bytes,’ or one ‘word,’ of information for a given row.
For a NOR logic arrangement of transistors, the memory cell transistors are arranged in a vertical column, are either uncoupled from a vertical metal line called a bit line or, are coupled in parallel to each other to the bit line. In addition, separate bit line exists for each vertical column of memory cell transistors. For example, sixteen bit lines exist for a word of bits (e.g. 16 binary digits or memory cell transistors in a row). The bit line communicates the actual logic level of the memory cell transistors to other portions of the ROM circuit. A y-decoder interprets an input address code to determine the appropriate bit line to which the address refers and then enables that bit line. With this grid of horizontal and vertical metal lines, each memory cell transistor, and its logic level, can be accessed by enabling the appropriate word line and appropriate bit line to which the desired memory cell transistor is coupled.
The gates of all the transistors in each row of a ROM may be suitably coupled to a horizontal conductor line referred to as a ‘word line.’ The word line is used to turn on the gates of all transistors grouped in that word line. Hence, the top word line, coupling sixteen memory cell transistors, may be referred to as word line
0
, the second word line, linking sixteen different memory cell transistors, may be referred to as word line
1
, and so on. An x-decoder may interpret an input address code to determine the appropriate word-line to which the address refers and then enables that word line.
Prior Art
FIG. 2
illustrates a pair of conventional memory cell transistors as may be commonly found within a ROM circuit
200
(e.g., ROM bank). Memory cell transistor
202
represents a logic level ‘0’ as its drain
203
couples bit line
204
to ground
290
. When gate
216
of memory cell transistor
202
is enabled by word line
214
, to which it is coupled, its source
218
, may be coupled to ground
290
. Thus, when bit line
204
is pre-charged, its voltage level may go to ground because of the coupling just described.
Conversely, memory cell transistor
206
may represent a logic level ‘1’ as its drain
207
is uncoupled from bit line
208
. When gate
212
of memory cell transistor
206
is enabled by word line
214
, to which it is coupled, its source
210
, coupled to ground
290
, may thereby be coupled to ground
290
via its drain
207
. Thus, when bit line
208
is pre-charged, its voltage level may remain at the voltage level of the pre-charge because of the coupling arrangement just described.
A data read operation (e.g., read request) of a ROM may typically be divided into three periods: bit line pre-charge, data sensing, and data output periods. At the beginning of the data read operation (i.e., the pre-charge period), all ROM banks, including the bit lines, may typically be pre-charged to a predetermined voltage (e.g., 1 V to 2 V) in order to enhance the sensing gain and increase the data sensing speed. Thereafter, the voltage level on the selected bit line within a ROM bank which is coupled with a selected memory cell may be sensed to determine whether the selected cell is an “on-cell” that presents a current path between a corresponding bit line and a voltage supply of a reference voltage (e.g., ground voltage), or “off-cell” during no current path between them. It is commonly assumed that the on-cell may be programmed to a logic “0” and the off-cell a logic “1.” Lastly, the sensed data may be output to exterior signal receiving devices.
One problem inherent in the above read method is that the method involves providing power to all available ROM banks. Particularly, the read method involves providing power to ROM banks which will not be accessed, and hence the provided power may be unnecessarily consumed. That is, it should be understood that in order to read from the ROM, all available ROM banks are generally first pre-charged during the pre-charge period, irrespective of whether the ROM bank is to be accessed. Therefore, a need exist for a method of accessing ROM banks and bit lines within ROM banks which will pre-charge only those ROM banks which are to be accessed, thereby, ensuring that the unnecessary consumption of power is minimized.
Conventional methods which have focused on pre-charging only select ROM banks or select bit lines within select ROM banks have encountered the problem often described as “cross talk.” Typical prior art methods which experience “cross-talk” include those described in U.S. Pat. No. 6,172,923 issued Jan. 9, 2001 to Lui and U.S. Pat. No. 6,185,147 issued Feb. 6, 2001 to Lui both incorporated herein by reference, in their entirety. A clear understanding of cross-talk may be had with continued reference to
FIG. 2
as discussed below.
FIG. 2
schematically illustrates a memory cell array of a conventional ROM, where the conventional sensing operation of a memory cell only references one memory cell
202
. This, in turn, means that, although not indicated in
FIG. 2
, the balance of the memory cells in the ROM circuit are left floating with whatever “residual charges” since those memory cells are charged during the read operation but not read (e.g. discharged).
Unfortunately, the residual charges left on disabled bit lines effects the read operation targeted at an enabled bit line. For example, the residual charge remaining on the disabled bit line will be sensed by the enabled bit line which retards the enabled bit line's ability to accept a pre-charge. This, in turn, will influence the phase and amplitude of th
Cheung Hugo
Chuang Shang-Yuan
Brady W. James
Swayze, Jr. W. Daniel
Tran M.
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