Solid-state imaging device

Details Solid-state imaging device Solid-state imaging device

1999-11-30

2003-01-14

Garber, Wendy R. (Department: 2612)

Television

Camera, system and detail

Solid-state image sensor

C348S302000

Reexamination Certificate

active

06507365

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device, and more particularly to the technique for improving the picture quality of an amplification type solid-state image pick-up device.
This application is based on Japanese Patent Applications No. 10-338936, filed Nov. 30, 1998, No. 11-021311, filed Jan. 29, 1999, No. 11-091720, filed Mar. 31, 1999, and No. 11-092964, filed Mar. 31, 1999, the entire content of which is incorporated herein by reference.
In recent years, a new market for image sensors, including digital still cameras, cameras built in personal computers, cellular phones, or the like, and TV conference cameras, has been getting wider. CCDs have been used as image sensors for TV cameras. CCDs, however, are unsuitable for a battery-powered portable apparatus with a camera, because they consume a lot of power. With this backdrop, solid-state image pick-up devices (CMOS image sensors) of the less-power-consumption amplification type (often called MOS type, CMOS type, or APS type) have been developed and commercialized as less-power-consumption solid-state image pick-up devices for mobile gears.
FIG. 1
shows an equivalent circuit of a first conventional amplification-type CMOS image sensor with a read circuit capable of reading a pixel signal pixel by pixel. In
FIG. 1
, unit cells
1
with one pixel/unit are arranged in a two-dimensional matrix in the cell area (imaging area). Each unit cell
1
is composed of, for example, four transistors Ta, Tb, Tc, Td and one photodiode PD. The ground potential is applied to the anode of the photodiode PD. To the cathode of the photodiode, one end of the read transistor (shutter gate transistor) Td is connected. The gate of the amplification transistor Tb is connected to the other end of the read transistor Td. One end of the vertical selection transistor (row selection transistor) Ta is connected to one end of the amplification transistor Tb. To the gate of the amplification transistor Tb, one end of the reset transistor Tc is connected.
In the cell area, a read line
4
connected in common to the gates of the read transistors Td of the unit cells in the same row, a vertical selection line
6
connected in common to the gates of the individual vertical selection transistors Ta of the unit cells in the same row, and a reset line
7
connected in common to the gates of the individual reset transistors Tc of the unit cells in the same row are formed in such a manner that they correspond to each row. Additionally, in the cell area, a vertical signal line VLIN connected in common to the other end of each amplification transistor Tb in the unit cells in the same column and a power supply line
9
connected in common to the other end of each reset transistor Tc and the other end of each vertical selection transistor Ta in the unit cells in the same column.
Furthermore, outside one end of the cell area, load transistors TL are arranged in the horizontal direction. They are connected between one end of each vertical signal line VLIN and the ground node. In addition, outside the other end of the cell area, noise canceler circuits are arranged in the horizontal direction. Each noise canceler circuit is composed of, for example, two transistors TSH, TCLP, and two capacitors Cc, Ct.
Horizontal selection transistors TH, which are connected to the other end of the corresponding vertical signal line via the corresponding noise canceler circuit, are arranged in the horizontal direction.
A horizontal signal line HLIN is connected in common to the other end of each horizontal selection transistor TH. To the horizontal signal line HLIN, a horizontal reset transistor (not shown) and an output amplification circuit AMP are connected.
Each noise canceler circuit is composed of a sample hold transistor TSH one end of which is connected to the other end of the vertical signal line VLIN, a coupling capacitor Cc one end of which is connected to the other end of the sample hold transistor TSH, a charge storage capacitor Ct connected between the other end of the coupling capacitor Cc and the ground node, and a potential clamp transistor TCLP connected to the junction node of the capacitors Cc and Ct. One end of the horizontal transistor TH is connected to the junction node of the capacitors Cc, Ct.
Furthermore, outside the cell area, there are provided a vertical shift register
2
for selecting the vertical selection lines in the cell area in a scanning manner, a horizontal shift register
3
for driving the horizontal selection transistors TH in a scanning manner, a timing generator
10
for generating various timing signals supplied to the noise canceler circuits, a bias generator
11
for generating specific bias potentials at one end of the potential clamp transistor TCLP of the noise canceler circuit, etc., and a pulse selector
2
a
for selectively controlling the output pulses of the vertical shift register
2
and thereby driving the vertical selection lines
6
in each row in the cell area in a scanning manner.
FIG. 2
is a timing waveform diagram to help explain an example of the operation of the CMOS image sensor shown in FIG.
1
. The operation of the CMOS image sensor of
FIG. 1
will be described by reference to FIG.
2
.
The incident light on each photodiode PD is photoelectrically converted into signal charge, which are stored in the photodiodes PD.
In a horizontal blanking period, when the signal charge in the photodiodes PD is read out from a row of unit cells, the signal (&phgr;ADDR pulse) on the vertical selection line
6
for the line to be selected is turned on to select each vertical signal line VLIN, thereby turning on one row of row selection transistors Ta. This causes a source follower circuit to operate in one row of unit cells. The source follower circuit is composed of a load transistor TL and an amplification transistor Tb to which a power supply potential VDD (e.g., 3.3V) is supplied via a row selection transistor Ta.
Then, the signal (&phgr;RESET pulse) on the reset line
7
is turned on in one row of unit cells, resetting the gate voltage of the amplification transistor Tb to a reference voltage for a specific period of time, which then outputs the reference voltage to the vertical signal line VLIN.
There are variations in the gate potential of the amplification transistor Tb that has been reset, which permits the reset potential of the vertical signal line VLIN at the other end to vary. To reset variations in the reset potential of each vertical signal line VLIN, the driving signal (&phgr;SH pulse) of the sample hold transistor TSH in the noise canceler circuit is turned on in advance (e.g., at the same time when the &phgr;ADDR pulse is turned on) and the driving signal (&phgr;CLP pulse) of the potential clamping transistor TCLP is kept on for a specific period of time after the reference voltage is outputted onto the vertical signal line VLIN, which thereby sets the voltage on the junction node of the capacitors Cc, Ct of the noise canceler circuit to the reference voltage VCC.
Next, after the &phgr;RESET pulse has been turned off, the read line
4
for a specific row is selected and the signal (&phgr;READ pulse) is turned on, turning on the read transistor Td to read the stored charge in the photodiode PD into the gate of the amplification transistor Tb, which varies the gate potential. The amplification transistor Tb outputs the voltage signal corresponding to the amount of change of the gate potential to the corresponding vertical signal line VLIN and noise canceler circuit.
Thereafter, the &phgr;SH pulse in the noise canceler circuit is turned off, which enables the signal component (the signal voltage from which noise has been removed) equivalent to the difference between the reference voltage read as described above and the signal voltage to be stored in the charge storage capacitor Ct even during the effective horizontal scanning period. Specifically, noise, such as variations in the reset potential of each vertical signal line VLIN originating in the cell area, applied to th

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