Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-08-07
2003-09-02
Tran, M. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S191000
Reexamination Certificate
active
06614713
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device having a function which allows a disturb test with good timing accuracy by a low-speed tester.
2. Description of the Background Art
A disturb test is a kind of known test for semiconductor memory devices. In the disturb test, a series of operations is performed as follows. A word line is raised to read out data in a memory cell onto a bit line. The data thus read is amplified by a sense amplifier, and is rewritten into the memory cell, and the word line is lowered. By the above operations, a memory cell on a neighboring unselected word line is disturbed.
In a conventional semiconductor memory device, an output (high-frequency signal) of an oscillator circuit arranged within the device is used as a trigger signal of the disturb test in order to use a low-speed tester for a short-cycle test, in which a period of each series of operations for the disturb test is reduced.
However, an influence by a process and test environments such as a temperature and a humidity cause variations in timing accuracy of the high-frequency signal forming the trigger. This results in a problem that the test cannot be performed accurately.
A testing burn-in apparatus which can test a large number of devices at a time may be used as the low-speed tester. In this case, the acceptance/rejection determination is performed in a scanning manner so that a long time is required for determining all the devices.
During the testing, a large number of devices are disturbed at a time so that the temperature in a burn-in tank rises, resulting in a strict environment for the devices. Accordingly, the device may enter an over-test specification state while the acceptance/rejection determination is being performed. This results in a problem that an acceptable device may be rejected depending on a margin.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a semiconductor memory device which allows a disturb test to be performed effectively with a good timing accuracy by a low-speed tester.
According to an aspect of the invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in rows and columns, and a plurality of word lines arranged corresponding to the plurality of rows of the memory cells; a test mode detecting circuit detecting in accordance with an external signal the fact that a test mode is set; and a control circuit being responsive to the output of the test mode detecting circuit and triggered by an external clock to perform control for conducting a disturb test on the memory cell array.
Preferably, the semiconductor memory device includes a clock buffer for receiving the external clock, and a row select control circuit for controlling selection of the row in the memory cell array. The control circuit is responsive to the output of the test mode detecting circuit to issue a signal determining operation timing of the row select control circuit based on the output of the clock buffer.
Preferably, the control circuit includes a refresh circuit issuing an automatic refresh signal for executing a refreshing operation of the memory cell array. The refresh circuit operates in a normal operation to issue the automatic refresh signal in response to an external command, and operates in the test mode to issue the automatic refresh signal in synchronization with the output of the clock buffer.
Preferably, the external clock includes a first external signal and a second external signal having the substantially same period as the first external signal. The device further comprises an internal clock generator generating an internal clock based on a phase difference between the first and second external signals. The control circuit performs the control for conducting the disturb test triggered by the internal clock.
Preferably, the device further includes a first buffer taking in the external clock, a second buffer taking in the external clock, and an internal clock generator generating an internal clock having double the frequency of the external clock in accordance with the outputs of the first and second buffers. The control circuit performs the control for conducting the disturb test triggered by the internal clock.
Preferably, the first and second buffers have the substantially same characteristics, and the internal clock generator generates the internal clock having the substantially constant pulse width based on the outputs of the first and second buffers.
Preferably, the external clock includes a first external signal and a second external signal having the substantially same period as the first external signal and the different phase from the first external signal. The device further comprises an internal clock generator generating an internal clock in accordance with the first and second external signals. The control circuit performs the control for conducting the disturb test triggered by the internal clock.
Preferably, the internal clock has pulses corresponding to rising and falling edges of the first external signal.
According to the semiconductor memory device described above, the disturb test triggered by the external clock is conducted on the memory cell array. Thereby, the test can be performed accurately even by a low-speed tester. By performing the refresh operation triggered by the external clock, the disturb test can be performed.
Further, the two external signals are used as the external clock, and the internal clock based on the phase difference between them is used as the trigger of the disturb test. Thereby, the short-cycle test can be effectively performed.
Further, the external clock is used to generate the internal clock having double the frequency, and the internal clock thus generated is used as the trigger of the disturb test. Thereby, the short-cycle test can be achieved effectively. In particular, by employing the buffer having the substantially constant characteristics, the internal clock having the uniform pulse width can be generated.
According to the semiconductor memory device described above, the internal clock is produced in accordance with the first and second external clocks having the same frequency and different phases, and is used as a trigger of the disturb test. In particular, in the case of the DDR-SDRAM, the internal clock has double the frequency of the first external clock so that the short-cycle test can be effectively performed.
Further, the invention provides a semiconductor memory device having a function of appropriately holding a state attained after a disturb test.
According to further another aspect of the invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in rows and columns, and a plurality of word lines arranged corresponding to the plurality of rows of the memory cells; a test mode detecting circuit detecting in accordance with an external signal the fact that a test mode is set; and a refresh control circuit including a refresh timer determining a refresh period in a refresh operation of the memory cell array, and controlling the refresh operation, the refresh timer in the test mode issuing an oscillation signal having a shorter period than that in a normal operation.
Preferably, the refresh timer includes a first signal generator generating a first oscillation signal, a second signal generator generating a second oscillation signal having a shorter period than the first oscillation signal, and a selector selectively issuing the first and second oscillation signals in accordance with an output of the test mode detecting circuit, and issuing the second oscillation signal as the oscillation signal in the test mode.
According to the semiconductor memory device described above, the refresh period is changed in the test mode. In particular, the refresh period is reduced. Owing to this, when the refresh operation is executed for holding the state after the disturb test, t
Asakura Mikio
Dosaka Katsumi
Tanizaki Tetsushi
Mitsubishi Denki & Kabushiki Kaisha
Tran M.
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