Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-02-06
2003-03-11
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C323S315000
Reexamination Certificate
active
06531914
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an internal voltage generation circuit which is provided in a semiconductor device and generates an internal power source of a predetermined voltage from an external power source. More particularly, the present invention relates to an internal voltage generation circuit which is provided in a semiconductor memory device and generates an internal voltage, in an amplification circuit having a feedback circuit, from a reference (constant) potential.
Recently, semiconductor devices or, more particularly, semiconductor memory devices have shown a tendency to become more dense and, as a result, the breakdown voltage of a transistor in such a device has fallen and, at the same time, the internal operation voltage has also been reduced in order to speed-up the operation and to reduce power consumption. Therefore it is necessary to reduce the voltage of a supplied power source and to generate an internal voltage, and a circuit that generates such an internal voltage is called an internal voltage generation circuit. In order to realize stable operation in such a circuit, it is necessary to generate a precise internal voltage, but because of variations in quality of products it is difficult to generate an internal voltage of required level without adjustment, therefore, a correction circuit is provided for each device for a precise adjustment of an internal voltage.
FIG. 1
illustrates the configuration of a general internal power source generation circuit.
As shown in
FIG. 1
, an internal power source generation circuit generates a predetermined potential level FVL in a temperature-compensated level generation circuit (a reference potential level generation circuit)
12
and inputs FVL to an inverting input terminal of an amplifier
14
. The output of the amplifier
14
is a reference voltage and is input to the gate of a P channel transistor
15
, and an internal voltage is output from the drain (node B) of the P channel transistor
15
. The output internal voltage is equal to the output of the amplifier
14
minus the voltage between the gate and the drain of the P channel transistor
15
.
The temperature-compensated level generation circuit
12
, which is widely known and thus a detailed description is omitted here, outputs a constant potential FVL irrespective of temperature by utilizing the fact that the resistance increases as the temperature increases but, on the contrary, the voltage between the gate and the source of a transistor decreases. The temperature-compensated level generation circuit
12
, however, has two convergent points, that is, the middle level and the ground level, therefore when the power of the device is turned on, a P channel transistor
13
is temporarily turned on, the output of the temperature-compensated level generation circuit
12
is connected to the high potential side of the power source, and after the conversion toward the middle level starts the P channel transistor
13
is turned off. Reference number
11
is an initiation signal generation circuit that generates a signal to be applied to the gate of the P channel transistor
13
. This circuit is also widely known, so a detailed description is omitted here. Because the initiation signal is used in other parts of the device, the initiation signal generated by the initiation signal generation circuit
11
is supplied to parts other than the internal voltage generation circuit.
A plurality of resistors
18
-
1
through
18
-
15
and
19
is connected in series between the output of the internal voltage generation circuit and the ground. Further, the non-inverting input terminal (node A) of the amplifier
14
is connected to the output of the internal voltage generation circuit and each connection node between each resistor via transfer gates
20
-
1
through
20
-
16
. A 4-bit selection signal can be set by cutting or not cutting each of the fuses F
1
through F
4
of a selection circuit
16
, and a state can be selected from among 16 states. A decoder
17
decodes a 4-bit selection signal and turns one of 16 outputs to H. This output is applied to the transfer gates
20
-
1
through
20
-
16
directly or via inverters
21
-
1
through
21
-
16
and turns on one of the transfer gates
20
-
1
through
20
-
16
.
If we assume that the resistors
18
-
1
through
18
-
16
have the same resistance of r and a resistor
19
has a resistance of R, the voltage of the non-inverting input terminal of the amplifier
14
is VA, and the internal voltage is VB, then VA/VB=(R+(16−n)r)/(R+15r), when the n (
1
-
16
) th transfer gate is brought into conduction. For example, when the first transfer gate is brought into conduction, VA/VB=1 and when the sixteenth transfer gate is brought into conduction, VA/VB=R/(R+15r). This makes it possible to feed back the internal voltage to the non-inverting input terminal, which is the reference of amplification (or reduction) of the amplifier
14
, and to adjust the internal voltage to a desired value because the ratio between the voltage VA of the non-inverting input terminal and the internal voltage can be set to one of 16 values.
In this case, an adjustable range is determined with the range of variations in devices being taken into consideration, and the adjustment width of a step is determined based on the required precision. Therefore, it is necessary to narrow the adjustment width of a step in order to increase the precision of the output voltage. In the sample in
FIG. 1
, the selection signal is 4-bit, that is, 16 settings are available, and the decoder
17
that selects one from 16 signal lines, which are distinguished from each other by the four fuses F
1
through F
4
(4-bit), and 16 sets of an inverter, a transfer gate, and a resistor are provided. In the internal voltage generation circuit in
FIG. 1
, as mentioned above, if the adjustment width is narrowed, that is, the number of correction points is increased, the size of the decoder
17
is enlarged accordingly, and the number of sets of inverter, transfer gate, and resistor is increased, for the same size of the adjustable range. Therefore a problem that the circuit area is increased appears if the number of correction points is increased.
Further, in the internal voltage generation circuit in
FIG. 1
, an initiation signal is applied to the gate of the P channel transistor
13
, which is connected between the output of the temperature-compensated level generation circuit
12
and the power source. Since the initiation signal generation circuit
11
detects the change in external power source and generates an initiation signal, in some cases the initiation signal is not generated even when the output of the temperature-compensated level generation circuit
12
temporarily drops due to such as an overload and begins to converge toward the ground level. In this case, a problem in that a desired internal voltage is not generated because the output of the temperature-compensated level generation circuit
12
converges toward the ground level occurs. This prevents the device from functioning properly because no internal voltage is generated.
SUMMARY OF THE INVENTION
The present invention solves these problems and the purpose of the present invention is to realize an internal voltage generation circuit, with a small area, that has many correction points and provides an output voltage with a high precision, and an internal voltage generation circuit that generates an internal voltage again without fail even if the output of the temperature-compensated level generation circuit is temporarily drops.
In order to realize the above-mentioned purpose, the internal voltage generation circuit of the present invention uses a feedback circuit in which resistors are connected in series and at least one of which has different value of resistance, and provides transfer gates in parallel with the resistors with different values of resistance. Since this configuration has a decoding function, a decoder can be omitted and the numb
Arent Fox Kintner & Plotkin & Kahn, PLLC
Cunningham Terry D.
Fujitsu Limited
Tra Quan
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