Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Reexamination Certificate
2001-09-24
2003-09-09
Dang, Trung (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With semiconductor element forming part
C257S693000, C257S701000, C438S125000, C438S126000, C438S121000, C438S928000
Reexamination Certificate
active
06617677
ABSTRACT:
The invention relates to an electric or electronic component comprising a carrier substrate of a semiconducting or insulating material, at least a recess, particularly a cavity or indentation provided in the carrier substrate, at least a component which is inserted into the recess and whose surface having at least an electrically conducting contact face faces the bottom and/or wall area of the recess and is contacted in the bottom and/or wall area of the recess, and at least a filling material by means of which the component inserted into the recess is sealed particularly with the edges of the recess.
The invention also relates to a method of manufacturing an electric or electronic component, the method comprising the steps of:
generating, particularly etching, at least a recess particularly at least a cavity or indentation, in a carrier substrate of a semiconducting or insulating material,
inserting at least a component, particularly at least an IC chip and/or at least an electrically active or electronically active (semiconductor) crystal, into the recess, in which the surface of the component having at least an electrically conducting contact face faces the bottom and/or wall area of the recess and is contacted in the bottom and/or wall area of the recess, and
sealing the component inserted into the recess, particularly with the edges of the recess, by means of at least a filling material.
Such a component and such a method are known from DE 197 20 300 A1. This document describes an electronic hybrid component with a co-planar chip on chip arrangement and with an electric rear side contact. A (silicon) carrier substrate of the component accommodates at least a cavity in which an electric insulation layer provided with a metal coating is present and in which at least a chip arranged on the carrier substrate is inserted and electrically contacted with the metal coating.
The method of manufacturing this component, known from DE 197 20 300 A1, allows the use of the conventional techniques in microelectronics and microsystem techniques and is specifically based on the fact that regions countersunk by anisotropic etching are generated in the carrier substrate and that structuring for generating the electrically conducting connection between the countersunk regions and the conductor track structures present on the co-planar surface is realized by a multiple metallization system. In this multiple metallization system, the countersunk structures are insulated after etching by oxidation or deposition of insulating layers on the carrier substrate. Subsequently, the countersunk regions and the carrier substrate are metallized. Then, the multiple metal layer is structured by means of a photolithographic process, while maintaining given minimum structure widths.
It is true that this known method has a series of advantages such as the manufacture of compact electronic components with extremely small dimensions (small building height, small fundamental surface, i.e. small foot print) of the housing (package) as well as with similar or even equal thermal properties of the chip and package based on material similarity or even material identity. In the conventional method, costly manufacturing steps which are liable to disturbance such as wirebond, enveloping and/or plating processes as well as the use of material for lead frames and wires are neither required. However, the known component and the known method of manufacturing this component prove to be inadequate in that, already at minor tilts and/or oblique positions of the chips in the recess of the carrier substrate, an orderly function of the component is no longer guaranteed, for example, because the electric contacting of the chip with the inner (bottom and/or wall area) of the recess is no longer completely established.
For the known components this means that, when producing the recess in the carrier substrate by means of, for example, anisotropic etching, no tolerances are fundamentally allowed, which renders the manufacture of the components known from DE 197 20 300 A1 very costly and leads to a high number of rejects.
It is an object of the invention to provide an electric or electronic component of the type described in the opening paragraph, as well as a method of manufacturing such a component, in which, in comparison with the state of the art, larger tolerances in the position and particularly the tilt of the component inserted into the recess are allowed without a detrimental effect on the electric contacting of the component with the inner side (bottom and/or wall area) of the recess. In this respect, the object of the present invention is also to provide greater tolerances in generating the recess in the carrier substrate.
This object is achieved by the characteristic features defined in claim 1 for an electric or electronic component as well as by the characteristic features defined in claim 14 for a method of manufacturing an electric or electronic component. Advantageous embodiments and essential further embodiments of the present invention are defined in the dependent claims.
In accordance with the teaching of the present invention, at least one electrically conducting contact track extending from the bottom and/or wall area of the recess to the surface of the carrier substrate is provided, which contact track is provided, particularly lithographically, before insertion of the component. To ensure a reliable connection between the relevant contact face of the component and the respective section of the contact track which is present in the bottom and/or wall area of the recess, at least an electrically conducting connection element is arranged in this interspace, by which connection element the contact face of the component is connected to the contact track section which is present in the bottom and/or wall area of the recess.
The provision of such connection elements has the advantage that it allows a given tilt of the component inserted into the recess without the electric contacting of the component with the inner side (bottom and/or wall area) of the recess suffering therefrom. In this case it is possible (but not necessary) that at least a part of the connection element is deformed so that a degree of freedom as regards the depth position and the tilt of the component is surprisingly realized. Those skilled in the art will appreciate that the tolerances in the manufacture of the recess into which the component is inserted can be chosen to be essentially wider than for conventional manufacturing methods. The above-mentioned advantages also involve a significant cost benefit in the manufacture of the carrier substrate and in the assembly, i.e. in the complete embedding of the component in the recess.
The present invention finally relates to a method of manufacturing a multitude of electric or electronic components, defined by the characteristic features in claim 29.
This method is based on a wafer of a carrier substrate of a semiconducting or insulating material in which, particularly by (anisotropic) etching, a multitude of recesses, particularly cavities or indentations, is generated at preferably equal mutual distances. After performing the above-mentioned steps of the method, in this case simultaneously or successively for the multitude of recesses with at least one component, a test of each component as well as printing the surface of the carrier substrate opposite the surface of the carrier substrate particularly by means of a laser may follow, if necessary, and finally the multitude of coherently manufactured components is split into individual pieces, particularly by mechanical and/or optical sawing of the wafer.
REFERENCES:
patent: 5963429 (1999-10-01), Chen
patent: 6133064 (2000-10-01), Nagarajan et al.
patent: 6191370 (2001-02-01), Oh
patent: 6441498 (2002-08-01), Song
patent: 19720300 (1997-12-01), None
Dang Trung
Koninklijke Philips Electronics , N.V.
Waxler Aaron
LandOfFree
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