Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-03-20
2003-04-29
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S214000, C438S494000, C438S588000
Reexamination Certificate
active
06555482
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits and their fabrication, and, more particularly, to complementary metal oxide semiconductor (CMOS) transistors having a dual-gate architecture.
BACKGROUND OF THE INVENTION
The present invention relates particularly to CMOS transistors formed on a silicon-on-insulator (SOI) substrate and having a dual-gate architecture with one of the gates “buried” in the SOI substrate. For such transistors, the use of dual metal gates is particularly desirable for reducing parasitic phenomena that could damage a semiconductor device. Such parasitic phenomena may include boron penetration, gate depletion, and the incorporation of certain high-permitivity dielectrics, for example.
The main problem caused by metal gates relates to the adjustment of the threshold voltage. This is because common materials used for N-channel MOS (NMOS) and P-channel MOS (PMOS) devices typically include so-called mid-gap materials. These materials shift the threshold voltage of an NMOS by ½E
g
toward positive values and that of a PMOS by ½E
g
toward negative values (where E
g
represents the band-gap energy of the material). For constant channel doping, this results in threshold voltages on the order of ±1 V for NMOS devices and PMOS devices, respectively. To bring these values back to conventional values on the order of ±0.5 V on long channels, counterdoping of the channels may be necessary. However, the buried channels obtained thereby have the disadvantage of being particularly sensitive to short-channel effects.
Various attempts have been made to eliminate the defects associated with buried channels, especially with respect to the use of a single mid-gap type material. Yet, these attempts typically use an SOIAS dual-gate architecture (see “Back-gated CMOS on SOIAS for dynamic threshold voltage control” by I. Y. Yang, C. Vieri, A. Chandraskasan and D. Antoniadis, pp. 822-31, IEEE T. Electron Devices, Vol. 44, May 1997). The principle of threshold voltage reduction by biasing the SOI substrate is also known (M. Haond and M. Tack, “Rapid electrical measurement of back oxide and silicon thickness in an SOI CMOS process”, IEEE T. Electron Devices, pp. 674-6, Vol. 38, March 1991). Antoniadis et al. have used this principle to obtain, in a process called “substrate bonding” (or wafer bonding) of two SOI substrates, p
+
and n
+
polysilicon buried gates aligned with the metal gates present on the front face.
The drawbacks of this process are that it requires two substrates, one of which is an SOI substrate (which is expensive), and expensive wafer bonding techniques. From an electrical standpoint, there may also be considerable leakage between the n
+
and p
+
buried gates since these are separated only by intrinsic polysilicon regions.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a process for fabricating dual-gate CMOS transistors that are simple and reliable.
Another object of the present invention is to provide dual-gate CMOS transistors and a process for fabrication thereof which allow for adjusting the voltage threshold of the NMOS and PMOS transistors by constant or dynamic biasing of a second buried gate. The efficacy of the buried gate may be enhanced by the use of a thin buried oxide provided by thermal oxidation, in the same way as the gate oxide of a conventional gate, for example.
Yet another object of the invention is to provide a simplified fabrication process requiring only a single SOI wafer (without any wafer bonding) for producing the above devices.
According to the invention, a process is for fabricating a MOS transistor including a semicondcutor channel region sandwiched between a first and a second gate. The first gate of the MOS transistor is formed within a silicon-on-insulator substrate. A semiconductor channel region is formed transversely surmounting the first gate, and semiconductor drain and source regions are formed on each side of the channel region, respectively. The semiconductor channel and semicondcutor source/drain regions are formed by epitaxy on the upper surface of the substrate. Furthermore, the channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and then at least partially filling the tunnel with a first dielectric. The second gate, which may be metal, for example, may be separated from the upper surface of the channel region by a second dielectric. The second gate may be formed on, and transverse to, the channel region.
More particularly, the first gate may be produced by forming isolating regions in the substrate defining an active zone and by doping the active zone. The semiconductor channel region may be formed by selective epitaxy of a layer of a first semiconductor on the upper surface of the active zone and by non-selective epitaxy on a layer of a second semiconductor. The first semiconductor may be selectively removable with respect to the substrate and with respect to the second semiconductor. Furthermore, the first and second semiconductor layers may be etched on the active surface to form a stack transversely surmounting the active zone and having two opposed sidewalls in which the first layer is exposed. Moreover, the first layer of the stack may be selectively etched to make the tunnel separating corresponding portions of the second semiconductor layer from the upper surface of the active zone. The first semiconductor may be a silicon-germanium alloy and the second semiconductor may be silicon.
Advantageously, the tunnel may be at least partially filled by forming a layer of the first dielectric on the semiconductor structure after the tunnel has been etched. The layer of the first dielectric may be formed by thermal oxidation or by deposition, for example. Preferably, the thickness of the layer of the first dielectric and the thickness of the layer of the first semiconductor are adjusted to completely fill the tunnel. This allows better control of the channel by the gate and better mechanical stability.
Additionally, the second gate may be formed by depositing a gate material on the layer of the first dielectric and by etching this layer to form the second gate. For example, the deposited gate material may be a metal or a Si
x
Ge
1−x
alloy (where 0≦x≦1) doped n
+
or p
+
depending on the channel type of the transistor. The portion of the layer of the first dielectric between the upper surface of the channel region and the lower surface of the second gate thus forms the second dielectric. The second gate may also be produced by a process of the “damascene” type, for example, which will readily be understood by those skilled in the art. Each of the first dielectric and the second dielectric may be chosen from at least one of SiO
2
, Si
3
N
4
, Al
2
O
3
, Ta
2
O
5
, HfO
2
, ZrO
2
, TiO
2
and any other dielectric having a high relative permitivity, e.g., greater than 50.
A semiconductor device according to the present invention, such as a MOS transistor, for example, is also provided and includes a channel region sandwiched between a first and a second gate. Further, the first gate is within a silicon-on-insulator substrate. The transistor also includes a semiconductor region surmounting the first gate and extending transversely to it, a channel region, and drain and source regions on each side of the channel region, respectively. The channel region may be isolated from the upper surface of the first gate by a tunnel at least partially filled with a first dielectric. Furthermore, the second gate may be on the channel region and transverse to the channel region. The second gate may be separated from the upper surface of the channel region by a second dielectric. Specifically, the tunnel preferably has a height of about 1 to 50 nm, e.g., about 20 nm.
REFERENCES:
patent: 5120666 (1992-06-01), Gotou
patent: 5349228 (1994-09-01), Neudeck et al.
patent: 5372959 (1994-12-01), Chan
patent: 5482877 (1996-01-01), Rhee
paten
Haond Michel
Jurczak Malgorzata
Skotnicki Thomas
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Brophy Jamie L.
Jorgenson Lisa K.
STMicroelectronics S.A.
Zarabian Amir
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