Method of forming electrodes for trench capacitors

Details Method of forming electrodes for trench capacitors Method of forming electrodes for trench capacitors

1992-07-30

1994-01-04

Fourson, George

Fishing, trapping, and vermin destroying

437919, 257535, H01L 2162

Patent

active

052759741

ABSTRACT:
A method is provided for forming electrodes of a trench capacitor for an integrated circuit in which the number of mask levels is reduced. The method is compatible with CMOS and Bipolar CMOS processes. After defining a trench in a substrate by a conventional photoengraving step and anisotropic etching, successive conformal layers of a first dielectric layer, a first conductive layer, and subsequent conformal dielectric layers and conformal conductive layers are deposited to fill the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Each of the conductive layers form an electrode. Coplanar areas of each of the conductive layers are exposed within the trench for formation of contacts to the electrodes. Advantageously, the trench has a wide portion and a narrow portion of smaller lateral dimension. The narrow portion of the trench is filled by the first conductive layer and after planarization provides an area of sufficiently large dimension for forming a contact to the first electrode. Contact to the second electrode is made in the first portion of the trench. Thus multiple electrodes for a trench capacitor are defined by a maskless process.

REFERENCES:
patent: 4577395 (1986-03-01), Shibata
patent: 4833094 (1989-05-01), Kenney
patent: 4905065 (1990-02-01), Selcuk et al.
"Depletion Trench Capacitor Technology for Megabit Level MOS DRAM", T. Morie et al IEEE E1. Dev Lett, vol. EDL-4, No. 11, Nov. 1983.
"A 4.2 um2 half-Vcc Sheath Plate Capacitor DRAM Cell with Self-aligned Buried Plate-Wiring" T. Kaga et al, IEDM, 87-328 (1987).
"Double-Stacked Capacitor with Self-Aligned Poly Source-Drain Transistor (DSP) Cell for Megabit DRAM", K. Tsukamoto et al, IEDM, 87-328 (1987).
"Process Technologies for High Density, High Speed 16 Megabit Dynamic Ram", F. Horiguchi et al., IEDM, 87-324 (1987).

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