Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2002-02-04
2003-04-08
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S701000
Reexamination Certificate
active
06545460
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor test system for testing semiconductor integrated circuits such as a large scale integrated (LSI) circuit, and more particularly, to a power source current measurement unit provided in a semiconductor test system which is capable of measuring a power source current of a device under test with high speed and high accuracy. The power source current measurement unit of the present invention is advantageously applicable to measurement of a power source current I
DD
of a CMOS integrated circuit.
BACKGROUND OF THE INVENTION
The power source (supply) current measurement unit of the present invention is used in a semiconductor test system for testing semiconductor integrated circuits such as LSIs (hereafter may also be referred to as “device under test”) Such a semiconductor test system performs mainly a functional test of the device under test, it also has a functionality for performing a DC parametric test in which DC voltage and DC current of the device under test are evaluated. The present invention is directed to a power source current measurement unit (DC test unit) for measuring a power source current of a device under test as a part of the DC parametric test.
The inventor of this invention has proposed a semiconductor test system based on notions of event (event based test system) which has an architecture different from a cyclized semiconductor test system (cycle based test system) widely used today. The power source current measurement unit of the present invention can be advantageously applied to the event based test system, however, it can also provide significant effects when used in the cycle based test system. Therefore, brief explanation will be made in the following as to the cycle based test system and event based test system.
FIG. 1A
is a block diagram showing an example of basic configuration in the cycle based test system. In this example, a test processor
11
is a dedicated processor provided within the semiconductor test system for controlling the operation of the test system through a tester bus. Based on pattern data from the test processor
11
, a pattern generator
12
provides timing data and waveform data to a timing generator
13
and a wave formatter
14
, respectively. A test pattern is produced by the wave formatter
14
with use of the waveform data from the pattern generator
12
and the timing data from the timing generator
13
, and the test pattern is supplied to a device under test (DUT)
19
through a driver
15
.
The DUT
19
generates an output signal in response to the test pattern which is provided to an analog comparator
16
in a pin electronics
20
. The output signal is converted to a logic signal by the analog comparator
16
with reference to a predetermined threshold voltage level. The logic signal is compared with expected value data from the pattern generator
12
by a logic comparator
17
. The result of the logic comparison is stored in a failure memory
18
corresponding to the address of the DUT
19
.
In such a cycle based test system, pattern data for producing test pattern must be described separately by waveform data, vector data, and timing data for each test cycle. Therefore, hardware and software involved in the cycle based test system become complicated, which makes it difficult to constitute a test system in such a way that each test pin is independent from the others.
FIG. 1B
is a schematic block diagram showing an example of basic structure in an event based test system. Description for further details of the event based test system is given in the U.S. patent application Ser. No. 09/406,300 and U.S. patent application Ser. No. 09/259,401 filed by the same inventor of this invention.
In this example, the event based test system includes a host computer
42
, a bus interface
43
, an internal bus
45
, an address control logic
48
, a failure memory
47
, an event memory consists of an event count memory
50
and an event vernier memory
51
, an event summing and scaling logic
52
, an event generator
24
, and a pin electronics
26
. A semiconductor device under test (DUT)
28
is connected to the pin electronics
26
.
An example of the host computer
42
is a work station having a UNIX operating system therein. The host computer
42
functions as a user interface to enable a user to instruct the start and stop operation of the test, to load a test program and other test conditions, or to perform test result analysis in the host computer. The host computer
42
interfaces with a hardware test system through the system bus
44
and the bus interface
43
.
The internal bus
45
is a bus in the hardware test system. An example of address control logic
48
is a tester processor which is exclusive to the hardware test system and is not accessible by a user. The address control logic
48
provides instructions to other functional blocks in the test system based on the test program and conditions from the host computer
42
. The failure memory
47
stores test results, such as failure information of the DUT
28
, in the addresses defined by the address control logic
48
. The information stored in the failure memory
47
is used in the failure analysis stage of the device under test.
The address control logic
48
provides address data to the event memory configured by the event count memory
50
and the event vernier memory
51
. The event memory stores event timing data describing each event (change point from “1” to “0” or from “0” to “1”) and its timing. For example, the event memory stores the timing data by two different types of data, one is integral part data showing an integer multiple of the reference clock, and fractional part data showing a fraction of the reference clock.
The event summing and scaling logic
52
is to produce data showing overall timing (delay time) of each event with respect to a predetermined reference point by summing the event timing data or modifying the timing data of each event by a scaling factor. The event generator
24
is to actually generate the test pattern (drive event) based on the overall timing data which is provided to the DUT
28
through the pin electronics
26
. By comparing the response output signal of the DUT
28
with the expected data pattern (sampling event), the particular output pin of the DUT
28
is evaluated by the test system.
In the event based test system, since the event data for producing the test pattern is described only by the timing data of events, the data structure of the event data is significantly simplified. Therefore, the event based test system can be configured by a plurality of test pins each being independent from the others.
In the test system described above, the structure of the pin electronics for applying the test pattern to the device under test and receiving the output signal of the device under test is basically the same in either the cycle based test system or the event based test system. Generally, the pin electronics is also provided with a measurement unit for performing a DC parametric test. In
FIG. 2
, the pin electronics
26
which deals with the drive event (test pattern), sampling event (strobe) and parameters for the test unit is shown in more detail along with the event generator
24
, pattern comparator
38
and the device under test (DUT
28
).
The event generator
24
produces drive events (test pattern) which are provided to an input pin of the DUT
28
through the driver
35
in the pin electronics
26
with a predetermined amplitude and a slew rate. The event generator
24
further produces a sampling event which is provided to the analog comparator
36
as a strobe signal for sampling an output signal of the DUT
28
. The output signal of the DUT
28
is converted to a logic signal by the analog comparator
36
when compared with predetermined reference voltages at the timing of the strobe signal. The logic signal at the output of the analog comparator
36
is compared with an expected logic pattern by the pattern comparator
38
.
A DC test unit
37
Advantest Corp.
Cuneo Kamand
Muramatsu & Associates
Tang Minh N.
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