Semiconductor device with dummy wiring layers

Details Semiconductor device with dummy wiring layers Semiconductor device with dummy wiring layers

2001-04-30

2003-01-07

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S773000, C257S774000

Reexamination Certificate

active

06504254

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a wiring layer.
2. Description of Related Art
Presently, wiring layers are formed in multiple layers in order to accomplish higher integration and further miniaturization of semiconductor devices. Interlayer dielectric layers are formed between wiring layers. The interlayer dielectric layers are planarized by a chemical mechanical polishing method (CMP method).
One technique is proposed to improve planarization of the interlayer dielectric layers by the CMP method. In the technique, as shown in
FIG. 5
, dummy wiring sections
130
are formed between densely formed metal wiring layers
120
a
and an isolated metal wiring layer
120
b
on the same level of the metal wiring layers
120
a
and
120
b
in the same step in which the metal wiring layers
120
a
and
120
b
are formed.
However, when the dummy wiring sections
130
are formed, the dummy wiring sections
130
overlap device elements (for example, wiring layers
114
) that are formed on a level below the dummy wiring sections
130
. In this case, when the exterior of the device elements (for example, the wiring layers
114
) formed on the level below the dummy wiring sections
130
is inspected, the observation by an optical microscope is difficult.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having dummy wiring sections formed therein.
A semiconductor device in accordance with one embodiment of the present invention has a wiring layer and a plurality of dummy wiring sections provided in the same level in which the wiring layer is formed, wherein the dummy wiring sections have at least one through hole.
In accordance with one embodiment of the present invention, at least one of the dummy wiring sections has a through hole. In one embodiment, the dummy wiring sections have a plurality of through holes. As a result, a plan area of the dummy wiring sections that overlap device elements formed on a level below the dummy wiring sections is reduced compared to the case where the dummy wiring sections do not have through holes. As a result, observation of the devices formed on the level below the dummy wiring sections by an optical microscope is facilitated.
In one embodiment, the peripheral section of each of the dummy wiring sections may be continuous.
In accordance with the present invention, the dummy wiring sections can be formed to have any one of the following plan configurations:
(1) The plan configuration of each of the dummy wiring sections may preferably be hexagonal.
When the plan configuration of each of the dummy wiring sections is hexagonal, the dummy wiring sections can be disposed highly densely. Also, when the dielectric layer is polished by the CMP method, the dummy wiring sections are strong against circular movements of the polishing cloth. In other words, the dummy wiring sections can more securely absorb polishing pressures applied in many different directions.
When the plan configuration of each of the dummy wiring sections is hexagonal, the plan configuration of the through hole may be the same as the plan configuration of each of the dummy wiring sections, in other words, may preferably be hexagonal. As a result, an opening area of the through hole at the dummy wiring section can be greater than an opening area provided by any other configurations.
Also, the plan configuration of the through hole may be triangle. As a result, through holes can be formed at locations corresponding to respective sides of the dummy wiring sections.
(2) The plan configuration of each of the dummy wiring sections may preferably be quadrilateral. When the plan configuration of each of the dummy wiring sections is quadrilateral, the configuration of the through hole may preferably be quadrilateral. In this case, because the plan configuration of the through hole is the same as the plan configuration of the dummy wiring section, i.e., quadrilateral, an opening area of the through hole at the dummy wiring section can be greater than an opening area that may be provided by any other configurations.
In one embodiment, the dummy wiring sections may be disposed at specified intervals. Preferably, the dummy wiring sections may be mutually disposed at equal intervals. When the dummy wiring sections are mutually disposed at equal intervals, the polishing pressure can be uniformly distributed over the dummy wiring sections.
The width of the peripheral section of each of the dummy wiring sections is determined in view of patterning accuracy, mechanical strength of the dummy wiring section and the like. For example, the peripheral section of each of the dummy wiring sections may have a width that is the minimum design wiring width (the minimum design rule) or greater but 2 &mgr;m or less. In the case of damascene wirings, when the width of the peripheral section of the dummy wiring section exceeds 2 &mgr;m, the amount of dishing at the dummy wiring section tends to become large.
The dummy wiring sections are formed such that adjacent ones of the dummy wiring sections are in contact with one another.
A semiconductor device in accordance with the present invention is particularly useful when the wiring layer is formed from metal.
Other features and advantages of the invention will be apparent from the following detailed description, taken in conjunction with the accompanying drawings that illustrate, by way of example, various features of embodiments of the invention.


REFERENCES:
patent: 4484212 (1984-11-01), Komatsu et al.
patent: 5442236 (1995-08-01), Fukawa
patent: 5663599 (1997-09-01), Lur
patent: 5763936 (1998-06-01), Yamaha et al.
patent: 6118145 (2000-09-01), Egawa
patent: 6208281 (2001-03-01), Jinbo et al.
patent: 6225697 (2001-05-01), Iguchi
patent: 6261883 (2001-07-01), Koubuchi et al.
patent: 2001/0040242 (2001-11-01), Koike

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