Mask programmable gate array base cell

Details Mask programmable gate array base cell Mask programmable gate array base cell

1991-04-08

1994-01-04

Kunemund, Robert

Fishing, trapping, and vermin destroying

437 51, 437 40, 257390, H01L 21265

Patent

active

052759628

ABSTRACT:
A method of forming a semiconductor gate array structure on a semiconductor substrate comprises the steps of forming a plurality of moat regions 12 and 14 where each of the moat regions 12 and 14 includes a channel region 22 and 28 and an insulating layer formed over the channel region 22 and 28. The moat regions separated by an insulating region 16. A plurality of gates 30 are formed wherein each of said gates 30 includes a first portion 30a over one of said channel regions 22, a second portion 30b over a channel region 28 adjacent to said one of said channel regions, and a third portion 30c over the insulating region 116 between said one of said channel regions. The gates 30 are formed such that each channel region is beneath one gate. The third portion 30a of a selected number of the gates is then etched to form the desired gate configuration. Finally, an additional insulating layer 160 may be formed over the array and contact holes formed in the layer such that interconnects may be created to form the desired transistor devices. Multiple levels of interconnects may be used. Modifications and variations, as well as an illustrative fabrication method are also disclosed.

REFERENCES:
patent: 4554729 (1985-11-01), Tanimura et al.
patent: 4975756 (1990-12-01), Haken et al.
patent: 5026657 (1991-06-01), Lee et al.
patent: 5081056 (1992-01-01), Mazzali et al.
patent: 5120571 (1992-06-01), Gill et al.
patent: 5136356 (1992-08-01), Sakuda et al.

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