Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Combined with diverse art device
Reexamination Certificate
1998-12-07
2003-01-21
Wachsman, Hal (Department: 2857)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Combined with diverse art device
C702S117000, C365S201000
Reexamination Certificate
active
06510443
ABSTRACT:
BACKGROUND
The invention relates generally to processing semiconductor devices having a number of non-functional input-output (I/O) pins.
During the manufacture of semiconductor devices, pin failures may occur that render the device partially inoperative. Rather than discarding such devices, two or more partially defective devices may be combined to form a component that, functionally, performs as one non-defective device. For example, a first random access memory (RAM) device having 16 I/O pins, of which 7 are inoperative, may be combined with one or more additional RAM devices (the collection of additional RAM devices having at least 7 operative I/O pins) to form a single memory component—the component functioning as a single 16 I/O pin RAM device.
A typical semiconductor device manufacturing and testing process is shown in FIG.
1
. Following device manufacture (block
100
), initial testing is performed to determine if the device is fully operational (block
102
). If the device is fully operational (the ‘yes’ prong of block
104
), it may be used immediately in the manufacture of electronic systems (block
106
). If the device is not fully operational (the ‘no’ prong of block
104
), it may be collected with other partially defective devices into lots (block
108
) that may undergo further testing (block
110
).
Semiconductor device testing may be performed by the combination of a test machine (hereinafter a “tester”) and a loader/unloader (hereinafter a “handler”). A tester may be used to determine which of a device's I/O pins are operational through, for example, electrical tests. Handlers, may be used to physically move devices into and out of a tester. Current handlers are capable of taking a device from a tester and selectively placing it into one of only a limited number of output positions or bins. For example, the Aetrium 3200 handler manufactured by Aetrium Incorporated, may place a tested device into one of ten output bins. This limitation may significantly restrict the use of partially operative devices. For example, a 16 I/O pin RAM device has more than 65,000 possible operative (or inoperative) I/O pin combinations. Since handlers may place components into only a small number of output bins (e.g., 10), however, only that number of operative I/O pin combinations may be categorized for subsequent use.
Referring again to
FIG. 1
, if during block
110
a device is found to have a pattern of operative I/O pins that correspond to one of a limited number of previously specified output patterns (the ‘yes’ prong of diamond
112
), it may be placed in the appropriate output bin and combined with other partially operative devices to form a functional component (block
114
). If a device's pattern of operational I/O pins fail to meet one of the previously specified output patterns (the ‘no’ prong of diamond
112
), it may be discarded (block
116
).
Because handlers can accommodate only a limited number of output bins, the number of operational output pin patterns specified in diamond
112
may be only a fraction of the total possible patterns. Thus, many devices that may be useful in the manufacture of functional components may be discarded. For example, if a specified I/O pin pattern requires that pins
0
through
7
and
12
through
16
be operative, then a device having operative I/O pins
1
through
8
and
12
through
16
may be discarded, even though it may be used to assemble functionally equivalent components as a device having the specified pattern of operative I/O pins.
Because the cost of discarding partially operational devices is becoming increasingly important in driving the cost of finished products, it would be beneficial to provide a mechanism that is capable of accommodating substantially all possible combinations of operative I/O pin patterns. It would be a further benefit to provide this capability without incurring the cost of modifying handlers to expand their output placement capacity.
SUMMARY
In one embodiment the invention provides a method to process partially defective semiconductor devices. The method includes identifying a parameter, identifying a first semiconductor device having a first defect (the first defect related to the parameter), and identifying a second semiconductor device having a second defect based on the identified parameter, the first defect, and the second defect. In one embodiment of the invention, the semiconductor devices are semiconductor memory devices which may be combined to form a component; the component capable of providing the function of a single fully operational semiconductor memory device. In another embodiment, the component may include more than two partially defective semiconductor devices.
A method in accordance with yet another embodiment of the invention includes testing a plurality of semiconductor memory devices (each semiconductor memory device having a plurality of input-output pins), identifying an operational state of each of the plurality of input-output pins for each of the plurality of semiconductor memory devices, generating a code indicating the operational state of each of the plurality of input-output pins for each of the plurality of semiconductor memory devices, and associating each generated code with an identifier of the semiconductor memory device tested to generate the code. The act of testing may comprise determining a number of operational input-output pins for each of the plurality of semiconductor memory devices. The act of generating a code may comprise generating a hexadecimal code indicating which input-output pins are operational. The act of associating each generated code with an identifier of the semiconductor memory device tested to generate the code may comprise storing the code and the unique identifier in a database record.
Methods in accordance with the invention may be stored in any media that is readable by a programmable control device such as a computer processor.
REFERENCES:
patent: 5400263 (1995-03-01), Rohrbaugh et al.
patent: 5726920 (1998-03-01), Chen et al.
patent: 5761145 (1998-06-01), Zagar et al.
patent: 6119049 (2000-09-01), Peddle
patent: 6161053 (2000-12-01), Chen et al.
Charlton David
Prak Sovandy
Micro)n Technology, Inc.
Trop Pruner & Hu P.C.
Wachsman Hal
LandOfFree
Processing semiconductor devices having some defective... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processing semiconductor devices having some defective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processing semiconductor devices having some defective... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3065086