Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-03-13
2003-01-07
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S737000, C257S738000, C257S780000, C257S693000, C257S692000, C257S691000, C257S784000, C257S786000, C257S787000, C257S783000, C257S676000, C361S774000, C361S777000
Reexamination Certificate
active
06504239
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a surface mount type and a resin sealed type semiconductor package.
This application is counterparts of Japanese patent applications, Serial Number 179641/1999, filed Jun. 25, 1999 and Serial Number 61631/2000, filed Mar. 7, 2000, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 1
is a top plan view showing a conventional semiconductor device.
FIG. 2
is a cross sectional view taken on line
2
-
2
′ of FIG.
1
.
The conventional semiconductor device has a base substrate
101
which is made of glass epoxy, ceramic or polyimide.
The base substrate
101
has a plurality of through holes
107
which penetrate the base substrate
101
and extend from a front surface of the base substrate
101
to a back surface of the base substrate
101
. A plurality of bonding pads
105
and a plurality of wiring patterns
103
which connect the bonding pads
105
to corresponding through hole
107
are formed on the front surface of the base substrate
101
.
A solder resist layer
109
is formed on a region of the front surface of the base substrate
101
except for regions where the bonding pads
105
are formed.
A semiconductor chip
113
is attached to the center of the front surface of the base substrate
101
through the solder resist layer
109
and an adhesive
111
such as a silver paste.
Electrodes formed on the semiconductor chip
113
are connected to corresponding bonding pad
105
by corresponding bonding wire
115
.
A sealing resin
117
is provided on a sealing area of the front surface of the base substrate
101
and thus the semiconductor chip
113
, the bonding wires
115
, the bonding pads
105
, the wiring patterns
103
and the through holes
107
are sealed by the sealing resin
117
.
A plurality of wiring patterns
119
connected to the through holes
107
are formed on the back surface of the base substrate
101
. A plurality of solder balls
121
are formed on the wiring patterns
119
.
The conventional semiconductor device as explained above is mounted on a mother board, not shown, such as an electric device.
However, the conventional semiconductor device has a problem explained hereinafter.
The semiconductor device is subjected to a thermal treatment process such as a reflow process when the semiconductor device is mounted on the mother board. In the thermal treatment process, moisture included in the adhesive
111
or moisture at an interface between the adhesive
111
and the solder resist layer
109
below the semiconductor chip
113
vaporizes. Stress occurs at the semiconductor device due to the moisture vaporizing. The stress is concentrated on a region between the semiconductor chip
113
and the center of sides of the base substrate
101
. Since the stress is particularly concentrated at a region between the semiconductor chip
113
and the center of long sides of the base substrate
101
, strong stress occurs at the sealing resin
117
, the solder resist layer
109
, and the base substrate
101
which are positioned at the region.
Therefore, as described below, there is a possibility that three defective modes occur.
1. a crack which occurs in the sealing resin
117
.
2. the solder resist layer
109
is peeled off from the base substrate
101
.
3. the sealing resin
117
is peeled off from the solder resist layer
109
.
Where such cracks and peeling off occur, there is a possibility that the semiconductor device become defective.
Consequently, there has been a need for an improved semiconductor device.
SUMMARY OF THE INVENTION
It is an object of the present invention is to provide a semiconductor device that may relieve stress effectively.
It is another object of the present invention is to provide a semiconductor device having a stable resin sealing process.
It is still another object of the present invention is to provide a semiconductor device having a simplified production process.
According to one aspect of the present invention, for achieving one or more of the above objects, there is provided a semiconductor device which includes a base substrate which has four sides, a first major surface and a second major surface opposite to the first major surface, a semiconductor chip which is mounted on the first major surface and has an electrode formed thereon. The semiconductor device also has a bonding pad which is formed on the first major surface, a wiring pattern which is formed on the first major surface and is connected to the wiring pattern and a bonding wire which connects the electrode of the semiconductor chip to the bonding pad. The semiconductor device also has a dummy pattern which is formed on the first major surface positioned between the center of one side and the semiconductor chip and a sealing resin which covers the semiconductor chip, the bonding wire, the bonding pad and a part of the dummy pattern.
According to another aspect of the present invention, for achieving one or more of the above objects, there is provided a semiconductor device which includes a base substrate which has four sides, a first major surface and a second major surface opposite to the first major surface and a semiconductor chip which is mounted on the first major surface and has an electrode formed thereon. The semiconductor device further includes a bonding pad which is formed on the first major surface, a wiring pattern which is formed on the first major surface and is connected to said wiring pattern and a bonding wire which connects the electrode of the semiconductor chip to the bonding pad. The semiconductor device further includes a dummy pattern which is formed on the first major surface positioned between the center of one side and the semiconductor chip and has an adhesion strength against a sealing resin lower than that of the semiconductor chip. The semiconductor device further includes the sealing resin which covers the semiconductor chip, the bonding wire, the bonding pad and a part of the dummy pattern.
According to still another aspect of the present invention, for achieving one or more of the above objects, there is provided a semiconductor device which includes a base substrate which has four sides, a first major surface and a second major surface opposite to the first major surface, a semiconductor chip which is mounted on the first major surface and has an electrode formed thereon. The semiconductor device also inculudes a bonding pad which is formed on the first major surface, a wiring pattern which is formed on the first major surface and is connected to the wiring pattern and a bonding wire which connects the electrode of the semiconductor chip to the bonding pad. The semiconductor device also includes an insulating layer which is formed over the first major surface except for the bonding pad and has a first region positioned between the center of one side of the base substrate and the semiconductor chip and second region, an adhesion strength of the first region against a sealing resin is lower than that of the second region. The semiconductor device also includes the sealing resin which covers the semiconductor chip, the bonding wire, the bonding pad, a part of the first region and a part of the second region.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.
REFERENCES:
patent: 5677575 (1997-10-01), Maeta et al.
patent: 6093971 (2000-07-01), Oppermann et al.
patent: 6198165 (2001-03-01), Yamaji et al.
patent: 6204559 (2001-03-01), Lin et al.
patent: 6229217 (2001-05-01), Fukui et al.
patent: 6242815 (2001-06-01), Hsu et al.
Oki Electric Industry Co. Ltd.
Volentine Francos P.L.L.C.
Williams Alexander O.
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