Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-04-30
2003-01-21
Graybill, David E. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S735000, C438S109000, C438S455000, C438S611000
Reexamination Certificate
active
06509639
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor packaging, and more particularly to a three-dimensional stacked semiconductor package with multiple semiconductor chips.
2. Description of the Related Art
In the field of electronic systems, there is a continuous need to increase performance and reduce size. This is largely achieved by improving semiconductor wafer manufacturing and semiconductor packaging technologies. Wafer manufacturing involves simultaneously fabricating numerous semiconductor chips as a batch on a silicon wafer using various etching, doping and depositing steps. After the wafer is complete, the chips are separated from one another and packaged.
Wafer manufacturing strives to reduce transistor or capacitor feature size in order to increase circuit density and enhance functionality. Device geometries with sub-micron line widths are so common that individual chips routinely contain millions of electronic devices. Reduced feature size has been quite successful in improving electronic systems, and continuous development is expected in the future. However, significant obstacles to further reduction in feature size are being encountered. These obstacles include defect density control, optical system resolution limits, and availability of processing material and equipment. Attention has therefore increasingly shifted to semiconductor packaging as a means to fulfill the relentless demands for enhanced system performance.
Semiconductor chips have input/output pads that must be connected to external circuitry in order to function as part of an electronic system. Traditionally, a single chip is individually housed in a single-chip package that is connected to other single-hip packages through a printed circuit board (or motherboard) which supplies power to the chips and provides signal routing among the chips. The single-chip package has connection media that is typically an array of metallic leads (e.g., a lead frame) or a support circuit (e.g., a substrate).
Several connection techniques are widely used for connecting the chip pads and the connection media. These include wire bonding, tape automated bonding (TAB) and flip-chip bonding. Wire bonding is by far the most common. In this approach, wires are bonded, one at a time, from the chip to external circuitry by thermocompression, thermosonic or ultrasonic processes. TAB involves bonding gold-bumped pads on the chip to external circuitry on a polymer tape using thermocompression bonding. TAB requires mechanical force such as pressure or a burst of ultrasonic vibration and elevated temperature to accomplish metallurgical welding between the wires or bumps and the designated surface. Flip-chip bonding involves providing pre-formed solder bumps on the pads, flipping the chip so that the pads face down and are aligned with and contact matching bond sites, and melting the solder bumps to wet the pads and the bond sites. After the solder reflows it is cooled down and solidified to form solder joints between the pads and the bond sites. Many variations exist on these basic methods.
A major advantage of flip-chip bonding over wiring bonding and TAB is that it provides shorter connection paths between the chip and the external circuitry, and therefore has better electrical characteristics such as less inductive noise, cross-talk, propagation delay and waveform distortion. In addition, flip-chip bonding requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space are used. While flip-chip technology has tremendous advantages over wire bonding and TAB, its cost and technical limitations are significant. For instance, the cost of forming bumps on the pads is significant In addition, an adhesive is normally underfilled between the chip and the support circuit to reduce stress on the solder joints due to thermal mismatch between the chip and the support circuit, and the underfilling process increases both manufacturing complexity and cost. Thus, none of these conventional connection techniques are entirely satisfactory.
Conventional single-chip packages typically have an area (or footprint) that is many times larger than the area of the chip, causing the printed circuit board to have excessively large area relative to the chips. However, as chip speeds increase, it becomes critical to position the chips close together since excessive signal transmission distance deteriorates signal integrity and propagation times. Other considerations such as manufacturing cost, reliability, heat transfer, moisture resistance, mounting and interconnect standardization, testability, and quality control have also become focal points of chip packaging.
Single-chip packages such as ball grid arrays (BGA) and chip scale packages (CSP) have been recently developed to address these considerations. Although these packages provide certain advantages, further size reduction and performance enhancement with these packages has been difficult to obtain due to physical dimension, design and manufacturing constraints.
Multichip modules (CM) or hybrid modules that package multiple chips on a common platform are an alternative to single-chip packages. These modules aim to achieve higher packaging density (lower volume and mass per chip), better signal integrity and reasonable manufacturing cost. Conventional multichip modules are essentially two-dimensional structures with multiple chips connected to a planar interconnection substrate which contains traces to supply power and signal transmission. Co-fired ceramic substrates have given way to organic-based substrates due to performance and cost advantages. However, since multichip modules utilize a planar interconnection substrate as the base, their effectiveness in packaging density is limited. For instance, a substrate transmission line that is 25 microns wide, 5 microns high and 10 millimeters long creates high line resistance and signal delays, which necessitates complex wiring rules in order to provide acceptable signal transmission distances and reasonable propagation delays.
Therefore, in order to create higher density packages, reduce area requirements and shorten signal transmission distances, three-dimensional packages with two, three or more vertically stacked chips are an emerging trend. Three-dimensional packages are particularly suitable for the electronic systems such as supercomputers and large cache memory devices which require high operating speed and high capacity in very limited space.
Three-dimensional packages generally follow two approaches. In one approach, individual chips are packaged in conventional single-chip packages and then the single-chip packages are vertically stacked and interconnected to one another. Single-chip packages stacked this way include thin small-outline packages (TSOP), ball grid arrays (BGA) and tape chip packages (TCP), and chip connections within the single-chip packages include wire bonding, TAB and flip-chip bonding. In another approach, leads are connected to the chips, and then the exposed leaded chips are vertically stacked and interconnected to one another. Most three-dimensional packages involve peripheral interconnection, but some provide area array interconnection. Numerous three-dimensional packages are reported in the literature.
U.S. Pat. Nos. 5,484,959, 5,514,907, 5,625,221 and 5,744,827 disclose three-dimensional packages in which stacked single-chip packages have large footprints that require large amounts of space. The single-chip packages also have long extended leads and associated wire bonds that limit electrical performance.
U.S. Pat. Nos. 5,854,507 and 6,072,233 disclose three-dimensional packages with stacked single-chip packages in which solder balls provide the primary vertical interconnections. The solder balls require large amounts of space.
U.S. Pat. No. 5,394,303 discloses a three-dimensional package in which the stacked single-chip packages include a flexible film with wiring layers wrapped around the chip. The f
Graybill David E.
Sigmond David M.
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