Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation
Reexamination Certificate
2001-12-21
2003-07-01
Mis, David C. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Tuning compensation
C331S017000, C331S03600C
Reexamination Certificate
active
06587005
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a phase locked loop (PLL) circuit having a variable output frequency and, more particularly, to an improvement of such a PLL circuit to have an adjustable output frequency.
(b) Description of the Related Art
PLL circuits are used in a variety of equipment for generating a local oscillation frequency. The PLL circuit should have lower dimensions and be manufactured at a lower cost by, for example, reducing the number of electronic components thereof, in view that the PLL circuit is now installed in a mobile telephone or a GPS receiver which is ever requested to have a lower weight and smaller dimensions.
FIG. 1
shows a conventional PLL circuit, which includes a VCO
41
, an N-divider
47
for dividing the output signal from the VCO
41
by a number of N to output an N-divided frequency signal, a reference frequency oscillator
46
, an R-divider
45
for dividing the reference frequency by a number of R to output an R-divided frequency signal, a register
48
for storing the number N, a register
49
for storing the number R, a phase comparator
44
for comparing the phase of the N-divided frequency signal against the phase of the R-divided frequency signal, a charge pump
43
for receiving the result of the comparison from the phase comparator
44
, and a loop filter (low-pass filter)
42
for passing the low-frequency component of the output from the charge pump
43
to generate a control voltage for the VCO
41
. Thus, a negative feedback loop is formed in the PLL circuit.
The control signal from the loop filter
42
is substantially an integrated signal of the difference between the phase of the output from the N-divider
48
and the phase of the output from the R-divider
49
. The output frequency from the VCO
41
is used as a local oscillation frequency signal during modulation or demodulation in a mobile telephone, for example.
The number N for dividing the output from the VCO
41
in the N-divider
47
is stored in the register
48
which receives the number N from a CPU disposed outside the PLL circuit.
A temperature-compensated crystal oscillator (TCXO) is generally used as the reference frequency oscillator
46
. The number R for dividing the reference frequency in the R-divider
45
is stored in the register
49
, which receives the number R from the external CPU. The numbers N and R are fed to the PLL circuit at the timing of a strobe signal.
The negative feedback loop of the PLL circuit allows the output oscillation frequency thereof to lock in a specified frequency defined by the reference frequency and the numbers N and R. More specifically, the output oscillation frequency f
VCO
from the VCO
41
is expressed by a function of the reference frequency f
tCXO
and the numbers N and R as follows:
f
VCO
=N×f
tXCO
/R
(1).
In general, the electronic components of the PLL circuit as described above can be integrated in a single LSI or LSI ship except for the VCO
41
and the reference frequency oscillator
46
. The reference frequency oscillator
46
is not integrated in the LSI because the crystal oscillator cannot be installed in the LSI and an accurate frequency oscillator having a temperature-compensated output frequency cannot be manufactured without the crystal oscillator.
The VCO
41
is not integrated in the LSI in the prior art because the output frequency of the VCO significantly fluctuates due to the fluctuation of the ambient temperature and the variance or scattering of the characteristics of the components thereof and an adjustment of the output frequency in the LSI for compensating the temperature fluctuation etc. to obtain an accurate oscillation frequency is difficult to achieve. Thus, the VCO
41
is generally disposed in a dedicated package, adjusted to generate an accurate frequency range and have suitable temperature characteristics before installation, and then installed in the PLL circuit as a dedicated component disposed outside the LSI.
Some proposals were presented recently to install the VCO in a LSI. For example, a literature entitled “A Low Phase Noise Monolithic VCO in SiGe BiCMOS” by J. M. Mourant, J. Imboronen and Teksbury, in digest of papers, pp 65-68, 2000 IEEE Radio Frequency Integrated Circuits Symposium, describes the VCO shown in FIG.
2
.
FIG. 3
also shows a simplified equivalent circuit diagram of the VCO of FIG.
2
. It is to be noted that
FIG. 3
shows only a single end of the equivalent circuit of
FIG. 2
, which has the configuration of a typical differential oscillator generally used in a LSI.
The differential oscillator shown in
FIG. 2
includes a plurality of pairs of pMOS transistors M
00
and M
10
, M
01
and M
11
, M
02
and M
12
, and M
03
and M
13
, wherein the sources and drains of each pair of pMOS transistors are connected together to form a serieal MOS capacitor pair. A control voltage CONT
0
, CONT
1
, CONT
2
or CONT
3
is applied to the common sources and drains of each transistor pair to vary the capacitance of each MOS capacitor, thereby forming a variable capacitance. These variable capacitances are shown by reference symbols C
0
, C
1
, C
2
and C
3
in FIG.
3
.
A pair of diodes D
04
and D
14
having cathodes connected to the gates of the respective pMOS transistors and anodes connected together. A tune voltage signal TUNE having a potential lower than VCC is applied to the anodes of the diodes D
04
and D
14
to reverse-bias the diodes D
04
and D
14
, thereby forming another capacitor pair having a variable capacitance, which is shown by a reference symbol C
4
in FIG.
3
.
A pair of bipolar transistors Q
01
and
11
are provided each having a base applied with a voltage which divides the collector voltage of the other of the bipolar transistors Q
01
and Q
11
by a capacitor C
05
or C
15
and a reactor L
12
or L
02
. Each of the bipolar transistors Q
01
and Q
11
thus has a negative resistance −R shown by the symbol Q
1
in
FIG. 3. A
pair of coils L
01
and L
11
are connected between the power source line VCC and the gates of respective pMOS transistors, corresponding to the inductance L
1
in FIG.
3
.
In
FIG. 3
, the inductance L
1
and the variable capacitances C
0
to C
4
form a parallel resonant circuit.
By achieving a negative resistance −R in the bipolar transistors which cancels the total resistance R of the resistance components of the variable capacitances C
0
to C
4
and the inductance L
1
in
FIG. 3
, the parallel resonant circuit oscillates at a resonance frequency f
OSC
:
f
OSC
=1/{2&pgr;(L
1
×(C
0
+C
1
+C
2
+C
3
+C
4
))
1/2
} (2).
Although the inductance L
1
is realized by the coil installed in a LSI and thus cannot be controlled for the value, the resonance frequency f
OSC
can be varied by controlling the control voltages CONT
0
, CONT
1
, CONT
2
and CONT
3
applied to the variable capacitances C
0
to C
3
and a tune voltage TUNE applied to the variable capacitance C
4
.
Referring to
FIG. 4
, among other variable capacitances, the variable capacitance C
4
reduces monotonically with the increase of the reverse-bias voltage due to the decrease of the depletion layer in the vicinity of the P-N junction. More specifically, the variable capacitance C
4
decreases in inverse proportion to the square root of the reverse-bias voltage. The reverse-bias voltage is generated between the VCC voltage and the tune voltage TUNE which is applied to the anodes of the diodes D
04
and D
14
in FIG.
2
. Thus, the resonance frequency decreases with the decrease of the tune voltage TUNE, and increases with the increase of the to tune voltage.
Each of the variable capacitances C
0
to C
3
shown in
FIG. 4
changes abruptly between a lower capacitance C
low
and a higher capacitance C
high
at a threshold voltage which resides between V
1
and V
0
of the bias voltage. These capacitances C
low
and C
high
are stable for each of the variable capacitances C
0
to C
3
. Accordingly, each of the variable ca
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