Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – For fault location
Reexamination Certificate
2001-05-10
2003-05-13
Le, N. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
For fault location
C324S551000
Reexamination Certificate
active
06563321
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for detecting line-shorts between conductive layers of a semiconductor device and the like.
2. Description of the Related Art
Generally, in a semiconductor device or a liquid crystal display (LCD) panel, when line-shorts are generated between conductive layers (wires), fatal electrical faults are caused in the semiconductor device or the LCD panel.
Therefore, it is essential to provide an automated line-shorts inspection method and apparatus for test conductive layers, so that the analysis of line-shorts is fed back to the manufacturing process, which would enhance the manufacturing yield.
In a first prior art method for detecting line-shorts of an LCD panel (see: JP-A-4-314032), a conductive tape is adhered to all gate bus lines and a conductive tape is adhered to all source bus lines. In this case, the conductive tapes and are connected by switches, respectively, to the ground.
In order to detect line-shorts around cross-over portions between the gate bus lines and the source bus lines, first, the respective switches are turned OFF and ON, and then, charged gate bus lines and grounded gate bus lines are monitored by a CRT or the like using a scanning electron microscope (SEM) inspection. In this case, the grounded gate bus lines are related to the line-shorts defects. Next, the respective switches are turned ON and OFF, and then, charged source bus lines and grounded source bus lines are monitored by a CRT or the like using the SEM inspection. In this case, the grounded source bus lines are related to the line-shorts defects. Thus, the locations of the line-shorts can be specified. This will be explained later in detail.
In the above-described first prior art method, however, if the test structures, i.e., the gate bus lines and the source bus lines are very-fined, it is difficult to adhere the conductive tapes thereto. Additionally, if the number of test structures formed on a transparent insulating substrate is large, the adhesion of conductive tapes thereto takes a long time, which would increase the burden of line-shorts inspection. Further, the transparent insulating substrate may be contaminated by the adhesion of the conductive tapes. Furthermore, since the SEM inspection requires vacuum equipment including a vacuum chamber, a vacuum pump, a vacuum meter and the like, the inspection apparatus therefor is expensive.
In a second prior art method for detecting line-shorts (see: Aakella V. S. Satya, “Microelectronic Test Structures for Rapid Automated Contactless Inline Defect Inspection”, IEEE Trans. on Semiconductor Manufacturing, Vol. 10, No, 3, pp. 384-389), parallel serpentine test conductive layers are provided to sandwich rows of floating rectangular pads. The test conductive layers are grounded at their ends through a substrate-contact.
In order to detect line-shorts between the conductive layers and the pads, electron beams of a low energy are scanned onto the pads. As a result, secondary-electron peak-intensity profile is displayed on a CRT or the like using the SEM inspection. In this case, the number of secondary electrons emitted from the pads having line-shorts with the conductive layers is made smaller. Thus, the locations of the line-shorts can be specified. This also will be explained later in detail.
In the second prior art method, however, in order to increase the S/N ratio, the area of each of the pads has to be increased, which cannot lengthen the conductive layers. As a result, the conductive layers are far from those of actual products. Also, the substrate-contact for grounding the conductive layers increases the manufacturing steps, which would increase the manufacturing cost. Further, since the SEM inspection requires vacuum equipment including a vacuum chamber, a vacuum pump, a vacuum meter and the like, the inspection apparatus therefor is expensive.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method and apparatus for detecting line-shorts of a semiconductor device capable of decreasing the burden of line-short inspection without being expensive.
According to the present invention, in a method for detecting a line-short between conductive layers, a potential (or temperature) distribution of the conductive layers is detected while applying a DC voltage thereto.
Also, in an apparatus for detecting a line-short between conductive layers a scanning potential (or thermal) microscope is provided to detect a potential (or temperature) distribution of the conductive layers while applying a DC voltage thereto.
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patent: 5877631 (1999-03-01), Takahashi
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patent: 6433561 (2002-08-01), Satya et al.
patent: 04-314032 (1992-11-01), None
SATYA; “Microelectronic Test Structures for Rapid Automated Contactless Inline Defect Inspection”; IEEE Transactions on Semiconductor Manufacturing; IEEE; vol. 10, No. 3; Aug. 1997; pp. 384-389.
Benson Walter
Foley & Lardner
Le N.
NEC Corporation
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