Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2001-01-31
2003-01-07
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S777000, C257S685000, C257S686000, C257S776000
Reexamination Certificate
active
06504244
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a wiring tape, which is adhered to the periphery of a semiconductor chip, and comparable in package size with a bare chip, and a semiconductor module including a plurality of such semiconductor devices densely arranged bidimensionally or tridimensionally.
Today, a multichip module made up of a plurality of density arranged semiconductor devices is under development. Various package configurations and mounting methods have already been proposed in relation to a multichip module. Conventional structures that implement the dense arrangement of semiconductor devices may be classified into specific types that will be described hereinafter.
In one type of structure, semiconductor devices are monodimensionally stacked on a circuit board in the vertical direction. Japanese Patent Laid-Open Publication No. 9-275183, for example, teaches a semiconductor device having outer connecting portions arranged on the top and bottom thereof. This kind of semiconductor devices may be stacked in the monodimensional configuration.
In another type of structure, semiconductor devices are not only stacked in the vertical direction, but also arranged side by side in the horizontal direction, i.e., in parallel to a circuit board. More specifically, a plurality of stacks of semiconductor devices are arranged side by side in one direction parallel to a circuit board or arranged side by side in two directions parallel to a circuit board, but perpendicular to each other. Let the former structure and latter structure be referred to as a bidimensional structure and a tridimensional structure, respectively.
U.S. Pat. No. 5,790,380 discloses a semiconductor device having the bidimensional structure and including a single flexible wiring board. The flexible wiring board is attached to the top, bottom and one side of a semiconductor chip by being part. Outer connecting portions are arranged on the one side of the chip. Also disclosed in this document are a semiconductor module having a second flexible wiring board attached to a stack of such semiconductor devices and a semiconductor module having a third wiring board attached to a plurality of such modules.
Japanese Patent Laid-Open Publication No. 10-335570 proposes a semiconductor module having a plurality of semiconductor devices arranged in the tridimensional structure. Specifically, each semiconductor device includes a polygonal insulation package accommodating a semiconductor chip in a cavity formed thereinside. Outer connecting portions, which are implemented by pins, are arranged on each surface of the package. The chip and outer connecting portions are electrically interconnected via conductive leads and bonding wires. Such semiconductor devices are arranged tridimensionally.
However, the semiconductor device taught in the previously mentioned Laid-Open Publication No. 9-275183 has outer connecting portions arranged only on the top and bottom of the semiconductor chip and therefore implements only the monodimensional structure. Dense arrangement available with this structure is limited. Further, even if a plurality of stacks of such semiconductor devices are positioned side by side, the semiconductor devices adjoining each other in the horizontal direction cannot be electrically connected. For example, the top semiconductor devices of two modules adjoining each other in the horizontal direction cannot be electrically interconnected without the intermediary of underlying semiconductor devices and a circuit board. This aggravates electric characteristics and brings about the more dense arrangement of a greater number of wirings due to the increasing density. The dense arrangement of wirings translates into a decrease in the width of the individual wiring and a decrease in the distance between nearby wirings, which, in turn, obstruct the design and production of wirings and increase the cost.
The bidimensional structure disclosed in U.S. Pat. No. 5,790,380 needs the second and third flexible wiring boards in addition to the first flexible wiring board because outer connecting portions are arranged only on one side of the chip, lowering the mounting density. Moreover, semiconductor devices cannot be interconnected without the intermediary of the second and third wiring boards and circuit board. This also results in the problem stated above in relation to Laid-Open Publication No. 9-275183.
A problem with the tridimensional structure proposed in Laid-Open Publication No. 10-335570 is that the polygonal insulation package is a substantial thickness and has the semiconductor chip bonded within the cavity by wire bonding. The resulting package sizes is therefore far greater than the chip size and critically obstructs dense mounting. Further, two semiconductor devices adjoining each other via an intermediate semiconductor device cannot be electrically interconnected without the intermediary of a semiconductor chip included in the intermediate semiconductor device. This increases the length a signal transfer path between the semiconductor devices to be interconnected and increases the load on the circuit design of a semiconductor chip.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide, at a low cost, bidimensional or tridimensional semiconductor module exhibiting desirable electric characteristics without aggravating wiring density, and a semiconductor device comparable in package size with a bare chip for constricting the semiconductor module.
In accordance with the present invention, a semiconductor device includes a semiconductor chip and a single wiring tape including a wiring layer having a preselected pattern. Outer connecting portions are arranged on the wiring tape while inner connecting portions are formed in the wiring tape and connected to electrodes included in the semiconductor chip. The wiring tape is bent at the edges of the semiconductor chip and adhered to at least three surfaces of the semiconductor chip. The outer connecting portions are arranged on the above at least three surfaces.
A semiconductor module including a plurality of semiconductor devices each having the above configuration is also disclosed.
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In-situ Multi-Step (IMS) CVD Process of (Ba,Sr) TiO3using Hot Wall Batch Type Reactor for DRAM Capacitor Dielectrics, M. Kiyotoshi et al.
Ichinose Michihiko
Takizawa Tomoko
Chu Chris
Katten Muchin Zavis & Rosenman
Lee Eddie
NEC Corporation
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