Method for etching organic film, method for fabricating...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S706000, C438S707000, C438S725000

Reexamination Certificate

active

06531402

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for etching an organic film, a method for fabricating a semiconductor device and a pattern formation method.
For the purpose of increasing the operation speed and lowering the consumption power of semiconductor devices, decrease of the dielectric constant of an interlayer insulating film included in a multi-level interconnect structure is recently regarded as significant. In particular, an organic film with a small dielectric constant can be easily formed by spin coating and curing, and hence is regarded as a very promising interlayer insulating film of the next generation. A well known example of the organic film with a small dielectric constant is an organic film including an aromatic polymer as a base.
In order to fabricate a device with a refined design rule of a gate length of 0.18 &mgr;m or less, a fine line processing technique of approximately 0.25 &mgr;m or less is necessary, and the design rule is considered to be more and more refined in the future. An organic film is generally patterned by plasma etching, but a fine pattern of 0.25 &mgr;m or less is very difficult to form from an organic film.
Known examples of the plasma etching employed for an organic film are a process using an etching gas including a N
2
gas and a H
2
gas as principal constituents (reported by M. Fukusawa, T. Hasegawa, S. Hirano and S. Kadomura in “Proc. Symp. Dry Process”, p. 175 (1998)) and a process using an etching gas including a NH
3
gas as a principal constituent (reported by M. Fukusawa, T. Tatsumi, T. Hasegawa, S. Hirano, K. Miyata and S. Kadomura in “Proc. Symp. Dry Process”, p. 221 (1999)).
CONVENTIONAL EXAMPLE 1
One of conventional etching methods will now be described as Conventional Example 1 referring to the result obtained by etching an organic film with a magnetic neutral loop discharge (NLD) plasma etching system manufactured by Ulvac Corporation (“SiO
2
Etching in magnetic neutral loop discharge plasma”, W. Chen, M. Itoh, T. Hayashi and T. Uchida, J. Vac. Sci. Technol., A16 (1998) 1594).
In Conventional Example 1, an organic film is etched by using an etching gas including a N
2
gas and a H
2
gas as principal constituents. The present inventors have carried out the etching process of Conventional Example 1 under the following conditions:
Plasma etching system: NLD plasma etching system
Volume flow ratio per minute in standard condition of etching gas:
N
2
:H
2
=50 ml:50 ml
Antenna power: 1000 W (13.56 MHz)
Bias power: 200 W (2 MHz)
Pressure: 0.4 Pa
Substrate cooling temperature: 0° C.
Etching time: 180 seconds
FIGS. 13A through 13D
are cross-sectional SEM photographs of holes formed under the aforementioned etching conditions in organic films, and the holes of
FIGS. 13A through 13D
have diameters of 0.16 &mgr;m, 0.18 &mgr;m, 0.24 &mgr;m and 0.40 &mgr;m, respectively. In
FIGS. 13A through 13D
, a reference numeral
101
denotes a silicon substrate, a reference numeral
102
denotes an organic film to be etched, and a reference numeral
103
denotes a mask pattern of a silicon oxide film used as a mask in etching the organic film
102
. The organic film
102
has a thickness of approximately 1.02 &mgr;m, and the mask pattern
103
has a thickness of approximately 240 nm.
Conventional Example 1 is described as a process using the etching gas including, as principal constituents, a N
2
gas and a H
2
gas, and another method for etching an organic film is proposed as a process using an etching gas including, as principal constituents, an O
2
gas, a N
2
gas and a C
2
H
4
gas (Genexh Rajagopalan, et al.; Abstra. The 1999 Joint International Meeting of ECS, Hawaii, October, 702 (1999)).
CONVENTIONAL EXAMPLE 2
Now, a method for fabricating a semiconductor device according to Conventional Example 2 will be described with reference to
FIGS. 14A and 14B
.
FIGS. 14A and 14B
show states where an organic film
105
formed on a semiconductor substrate
104
is subjected to plasma etching by using a mask pattern
106
of, for example, a silicon oxide film formed on the organic film
105
.
FIG. 14A
shows a state in the middle of the plasma etching and
FIG. 14B
shows a state after completing the plasma etching. In
FIGS. 14A and 14B
, a reference numeral
107
denotes a first recess having a small diameter and a reference numeral
108
denotes a second recess having a comparatively large diameter. Although not shown in the drawings, a metal material film is formed over the mask pattern
106
so as to fill the first recess
107
and the second recess
108
, and a portion of the metal material film formed on the mask pattern
106
is removed by, for example, chemical mechanical polishing (CMP), so as to form a connection plug or a metal interconnect from the metal material film.
As is shown in
FIG. 14A
, the etching rate of the first recess
107
having a small diameter is lower than the etching rate of the second recess
108
having a comparatively large diameter.
Also, as is shown in
FIG. 14B
, the etching time required for completing etching the first recess
107
is generally calculated on the basis of the etching rate of the first recess
107
, and over-etching of several tens % is generally conducted in addition to the calculated etching time so as to completely remove the organic film
105
remaining on the semiconductor substrate
104
within the recess.
CONVENTIONAL EXAMPLE 3
As methods of forming a mask pattern through dry development, a top surface imaging (TSI) process, a three-layer resist process and the like are known.
In the top surface imaging process, a surface of an organic film resulting from pattern exposure is subjected to silylation, so as to selectively form a silylated layer on an exposed or unexposed portion of the organic film. Then, the organic film is subjected to dry development using the silylated layer as a mask, so as to form a mask pattern.
In the three-layer resist process, after an organic film and a silicon oxide film are successively formed on a semiconductor substrate, a thin resist pattern is formed on the silicon oxide film. Then, the silicon oxide film is subjected to plasma etching by using the resist pattern as a mask, so as to form an oxide film pattern by transferring the resist pattern onto the silicon oxide film. Next, the organic film is subjected to dry development (plasma etching) by using the oxide film pattern. Thus, a fine organic film pattern having a high aspect ratio is formed from the organic film.
Furthermore, an etch target film formed on the semiconductor substrate is etched by using a two-layer mask pattern consisting of the oxide film pattern and the organic film pattern. In this manner, a fine pattern that cannot be resolved by a single layer resist can be formed in the etch target film.
The present inventors have carried out the three-layer resist process, as a mask pattern formation method for Conventional Example 3, by using an etching gas including an O
2
gas under the following etching conditions:
Plasma etching system: NLD plasma etching system
Flow rate per minute in standard condition of etching gas: O
2
=90 ml
Antenna power: 1000 W (13.56 MHz)
Bias power: 400 W (2 MHz)
Pressure: 0.133 Pa
Substrate cooling temperature: 0° C.
Etching time: 4 minutes
FIGS. 16A and 16B
are cross-sectional SEM photographs of holes formed in an organic film pattern by the pattern formation method for Conventional Example 3, and the holes of
FIGS. 16A and 16B
have diameters of 0.18 &mgr;m and 0.4 &mgr;m, respectively. In
FIGS. 16A and 16B
, a reference numeral
111
denotes a silicon substrate, a reference numeral
110
denotes an organic film pattern formed from an organic film, and a reference numeral
109
denotes an oxide film pattern formed from a silicon oxide film. A resist pattern present on the oxide film pattern
109
is eliminated during the formation of the organic film pattern
110
through the dry development, and hence, an etch target film deposited on the silicon substrate
111
is etched by using the two-layer mask patter

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