Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-10-17
2003-05-06
Patel, Rajnikant B. (Department: 2838)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000, C257S355000, C327S313000
Reexamination Certificate
active
06560081
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device circuits and, in particular, to electrostatic discharge protection circuits for use with integrated circuits.
2. Description of the Related Art
A major reliability problem for integrated circuits is the provision of adequate protection against Electrostatic Discharge (ESD) or other excess voltage events. Therefore, specialized ESD protection devices (also known as ESD protection circuits) are commonly employed in an integrated circuit (IC) to protect electronic devices in the IC from spurious pulses of excessive voltage (i.e., an ESD event, Human Body Model [HBM] event, or Electrical Overstress [EOS] event). See,. for example, S. M. Sze,
Electrostatic Discharge Damage,
in VLSI Technology, 648-650 (McGraw Hill, 1988). A variety of conventional ESD protection devices that make extensive use of diodes, metal-oxide semiconductor field effect transistors (MOSFETs) and bipolar transistors are known in the field.
Conventional bipolar transistor-based ESD protection devices include, for example, bipolar transistor-based transient and bipolar transistor-based static ESD protection devices (e.g., grounded base bipolar transistor-based ESD protection devices and Zener Triggered bipolar transistor-based ESD protection devices). Descriptions of these and other conventional ESD protection devices are available in G. Croft and J. Bernier,
ESD Protection Techniques for High Frequency Integrated Circuits,
Microelectronics Reliability 38, 1681-1689 (1998); J. Z. Chen et al.,
Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS/Bipolar Circuits,
34
th
Annual IEEE International Reliability Physics Symposium Proceedings, 227-232 (1996); J. C. Bernier et al.,
A Process Independent ESD Design Methodology,
IEEE International Symposium on Circuits and Systems Proceedings 1, 218-221 (1999); W. D. Mack et al.,
New ESD Protection Schemes for BiCMOS Processes with Application to Cellular Radio Designs,
IEEE International Symposium on Circuits and Systems 6, 2699-2702 (1992); Ming-Dou Ker et. Al.,
Design on the Low
-
Leakage Diode String for Using in the Power
-
Rail ESD Clamp Circuits in a
0.35-&mgr;m
Silicide CMOS Process,
IEEE Transactions on Solid-State Circuits 35, 601-611 (2000); and Julian Z. Chen et al.,
Bipolar SCR ESD Protection Circuit for High Speed Submicron Bipolar/BiCMOS Circuits,
IEEE International Electron Devices Meeting Technical Digest, 337-340 (1995), each of which is hereby fully incorporated by reference.
FIG. 1
is an electrical schematic illustrating a conventional Zener Triggered bipolar transistor-based ESD protection circuit. This conventional Zener Triggered bipolar transistor-based ESD protection circuit requires the use of a Zener diode that essentially operates in avalanche breakdown (although true Zener tunneling breakdown will occur prior to avalanche breakdown). The Zener diode must, therefore, possess an avalanche breakdown voltage equivalent to the voltage of the ESD event against which the circuit is protecting. For example, if the Zener diode is a 6V Zener diode, the circuit can protect against an ESD event voltage of 6 volts or higher. The conventional Zener Triggered bipolar transistor-based ESD protection circuit cannot, therefore, be easily adjusted to provide ESD event protection against ESD event voltages other than those equal to or greater than its Zener diode avalanche breakdown voltage.
Still needed in the field, therefore, is an ESD protection circuit that is easily configured to provide ESD event protection against a range of ESD event voltages. The ESD protection circuit should also be compatible with high frequency ICs.
SUMMARY OF THE INVENTION
The present invention provides an ESD protection circuit that can be easily configured to provide ESD event protection against a range of ESD event voltages. The ESD protection circuit is also compatible with high frequency ICs.
ESD protection circuits according to the present invention include an input terminal configured to receive an ESD event signal and a diode sub-circuit. The diode sub-circuit includes at least one diode, a diode input node and a diode output node. The diode sub-circuit is configured to receive the ESD event signal from the input terminal and to operate under forward bias conditions to provide a diode output signal at the diode output node.
ESD protection circuits according to the present invention also include a bipolar junction transistor (e.g., a Si—Ge bipolar junction transistor [BJT]) with a base, a collector and an emitter. The emitter is configured to receive the ESD event signal from the input terminal, while the base is configured to receive the diode output signal from the diode output node. Also included are a resistor with a resistor input node, a resistor output node and an output terminal. The resistor input node is electrically connected to the diode output node and the output terminal is electrically connected to the resistor output node, the emitter and ground.
By predetermining the number, the electrical characteristics (e.g., forward bias voltage) and the electrical interconnection of the diodes, the circuit can be adapted to provide ESD protection against a range of ESD event voltages. Since high frequency BJTs can be employed in the ESD protection circuit, an ESD protection circuit according to the present invention is also compatible for use with high frequency ICs.
REFERENCES:
patent: 3394268 (1968-07-01), Murphy
patent: 3934159 (1976-01-01), Nomiya et al.
patent: 4220876 (1980-09-01), Ray
patent: 4303831 (1981-12-01), El Hamamsy
patent: 5010380 (1991-04-01), Avery
patent: 5079608 (1992-01-01), Wodarczyk et al.
patent: 5412527 (1995-05-01), Husher
G. Croft and J. Bernier,ESD Protection Techniques for High Frequency Integrated Circuits, Microelectronics Reliability 38, 1998, pp. 1681-1689 Jul. 9, 1998.
J.Z. Chen et al.,Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS-Bipolar Circuits, 34th Annaul IEEE International Reliability Physics Symposium Proceedings, 1996, pp. 227-232, No Date.
J. C. Bernieret et al.,A Process Independent ESD Design MethodologyIEEE International Sympsium on Circuits and Systems Proceedings 1, 1999, pp. 218-221, No Date.
W.D. Mack et al.,New ESD Protection Schemes for BiCMOS Processes with Application to Cellular Radio Designs, IEEE International Symposium on Circuits and Systems 6, 1992, pp. 2699-2702.
Ming-Dou Ker et al.,Design on the Low-Leakage Diode String for Using in the Power-Rail ESD Clamp Circuits in a 0.35-um Silicide CMOS Process, IEEE Transactions on Solid-State Circuits 35, 2000, pp. 601-611.
Julian Z. Chen et al.,Bipolar SCR ESD Protection Circuit for High Speed Submicron Bipolar/BiCMOS Circuits, IEEE International Electron Devices Meeting Technical Digest, 1995, pp. 337-340.
Hopper Peter J.
Vashchenko Vladislav
National Semiconductor Corporation
Patel Rajnikant B.
Pickering Mark C.
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