Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device
Reexamination Certificate
2002-02-04
2003-07-22
Nguyen, Tuan H. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
C257S197000, C257S200000
Reexamination Certificate
active
06597022
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of fabrication of semiconductor devices. More specifically, the invention relates to the fabrication of semiconductor heterojunction bipolar transistors.
2. Background Art
In a heterojunction bipolar transistor, or HBT, a thin silicon-germanium (“SiGe”) layer is grown as the base of a bipolar transistor on a silicon wafer. The SiGe HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Speed and frequency response can be compared by the cutoff frequency which, simply stated, is the frequency where the gain of a transistor is considerably reduced. Cutoff frequencies in excess of 100 GHz have been achieved for the HBT, which are comparable to the more expensive GaAs. Previously, silicon-only devices have not been competitive for use where very high speed and frequency response are required.
The higher gain, speed and frequency response of the SiGe HBT are possible due to certain advantages of silicon- germanium, such as a narrower band gap and reduced resistivity. These advantages make silicon-germanium devices more competitive than silicon-only devices in areas of technology where high speed and high frequency response are required.
The advantages of high speed and high frequency response discussed above require, among other things, that certain dimensions, such as the width of the emitter, be very accurately controlled. A dimension, which critically affects the performance of devices on a semiconductor, such as the emitter width in a HBT, is generally referred to as critical dimension, or “CD.” Chip manufacturers calculate a CD budget for the semiconductor wafer, i.e. the allowable variation of critical dimensions on the wafer surface. As device feature sizes become smaller, it becomes more difficult to accurately control the dimensions of features such as emitter width.
Control of feature dimensions is difficult because every step in the photolithographic patterning process contributes variations. For example, unwanted variation in dimension of a feature may be caused by defects in the photomask; To reflectivity of a surface of the material below the photoresist, referred to as “subsurface reflectivity,” which causes scattering of the light used to expose the photoresist; adhesion problems between an antireflective coating and the wafer and photomask; or poor matching of index of refraction between an antireflective coating and the photomask. Thus, as feature sizes become smaller, the CD budget becomes stricter, necessitating more accurate control over critical dimensions, for example the emitter width of the SiGe HBT. In the case of the SiGe NPN HBT control of the emitter width is essential to the performance of the device.
In one approach to forming a polycrystalline silicon emitter with critical dimension control in a SiGe HBT, an emitter window opening is formed in a layer of silicon oxynitride, which is then selectively etched to the single crystal SiGe base. However, selectively etching silicon oxynitride to the single crystal SiGe base is difficult and can cause pitting and recessing damage to the SiGe base. In addition, unwanted silicon oxynitride is difficult to remove after the emitter has been formed. Unremwved silicon oxynitride can degrade the performance of the SiGe HBT. Thus, use of silicon oxynitride does not provide a satisfactory solution to the problem of forming a polycrystalline silicon emitter with critical dimension control.
Another approach to forming a polycrystalline silicon emitter with critical dimension control in a SiGe HBT utilizes silicon dioxide (“oxide”) spacers formed on a base oxide layer on the top surface of the SiGe HBT. A polysilicon post is formed between the two oxide spacers, and the polysilicon post and oxide spacers are coveted by an oxide layer, an amorphous silicon layer, and an oxynitride layer. An emitter window opening is created by patterning and etching the oxynitride, amorphous silicon, silicon dioxide layer, and the polysilicon post. The oxide layer in the emitter Window opening is then etched to expose the top surface of the base. The emitter of the SiGe HBT can then be formed by depositing polycrystalline silicon on the top surface of the base. However, in the process of etching the base oxide layer, the silicon dioxide spacers are also laterally etched. As a result, the above approach undesirably widens the emitter window opening. Thus, the use of silicon dioxide spacers does not provide a satisfactory solution to the problem of forming an HBT emitter with critical dimension control.
Thus, there is a need in the art for an emitter structure in an HBT having a precisely controlled emitter width.
SUMMARY OF THE INVENTION
The present invention is directed method for controlling critical dimension in an HBT emitter and related structure. The present invention addresses and resolves the need in the art for a polycrystalline silicon emitter structure in an HBT that achieves a precisely controlled emitter width.
According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor, for example, may be an NPN silicon-germanium heterojunction bipolar transistor. The heterojunction bipolar transistor further comprises a first nitride spacer and a second nitride spacer situated on the base, where the first nitride spacer and the second nitride spacer are separated by a distance substantially equal to a critical dimension. For example, the first nitride spacer and the second nitride spacer may comprise LPCVD or RTCVD silicon nitride. The heterojunction bipolar transistor might further comprise an etch stop layer situated on the top surface of the base and below the first and second spacers. The etch stop layer can, for example, comprise silicon oxide.
According to this exemplary embodiment, the heterojunction bipolar transistor further comprises an emitter situated between said first nitride spacer and said second nitride spacer, where the emitter has a width substantially equal to the critical dimension. The emitter may, for example, comprise polycrystalline silicon. The heterojunction bipolar transistor might further comprise an amorphous layer situated on the first and second nitride spacer. For example, the amorphous layer may, for example, comprise amorphous silicon. The heterojunction bipolar transistor might further comprise an antireflective coating layer situated on the amorphous layer. The antireflective coating layer may, for example, comprise silicon oxynitride. In another embodiment, the present invention is a method that achieves the above-described heterojunction bipolar transistor.
REFERENCES:
patent: 6251738 (2001-06-01), Huang
patent: 6316818 (2001-11-01), Marty et al.
patent: 6337494 (2002-01-01), Ryum et al.
patent: 6384469 (2002-05-01), Chantre
Farjami & Farjami LLP
Newport Fab LLC
Nguyen Tuan H.
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