D/A converter circuit and semiconductor device

Details D/A converter circuit and semiconductor device D/A converter circuit and semiconductor device

2001-11-21

2003-09-02

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S154000, C341S136000, C341S150000

Reexamination Certificate

active

06614376

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a D/A converter (digital/analog converter) circuit (DAC). In particular, the present invention relates to a DAC used in a driver circuit of a semiconductor device. Further, the present invention relates to a semiconductor device using the DAC.
2. Description of the Related Art
Research and development of thin film transistors (TFTs) using polycrystalline silicon films formed on glass substrates as active layers has been advancing briskly in recent years. A TFT using a polycrystalline silicon film has a mobility which is two orders of magnitude or more higher than the mobility of a TFT that uses an amorphous silicon film, and therefore the electric current value necessary for circuit operation can be sufficiently maintained even if the gate width of the TFT becomes small and highly defined. Accordingly, it is possible to realize a “system on panel” in which a pixel portion of a matrix type flat panel display and a driver circuit are integrally formed on the same substrate.
Cost reductions are made possible with the “system on panel” because the number of fabricating steps and inspection steps of the display can be reduced. Further, it is possible to make the flat panel display smaller in size and with more high definition.
An issue relating to advances in making flat panel displays even smaller and higher definition is the realization of a DAC capable of high speed operation and occupying only a small amount of surface area on a substrate.
Several types of DACs exist, and capacitance divided types and resistance divided types can be given as typical. Compared to resistance divided DACs, capacitance divided DACs is capable of high speed operation with a relatively small surface area.
Shown in
FIG. 11
is an example of a conventional capacitance divided DAC. The conventional capacitance divided DAC shown in
FIG. 11
has n switches SW[1] to SW[n] controlled by each bit D
1
to D
n
of an n-bit digital signal, and n capacitors C, 2C, . . . , 2
n−1
C, connected to each switch, and a reset switch SW
R
. Further, an electric power source A (electric potential V
A
) and an electric power source B (electric potential V
B
) are connected to this conventional DAC. The electric power source A and the electric power source B are maintained at different electric potentials. Furthermore, the electric potential V
OUT
of an analog signal output from the DAC is imparted to an output line.
Corresponding bits of a digital signal are input to the switches SW[
1
] to SW[n], respectively. Selection of whether each of the capacitors is connected to the electric power source A or to the electric power source B is then made in accordance with information indicating 0 or 1 contained in the input digital signal.
Operation of the conventional DAC is explained in order. The conventional DAC can be explained by dividing it into reset periods T
R
and write in periods T
A
.
First, the reset switch SW
R
is closed during a reset period T
R
. Further, all of the switches SW[
1
] to SW[n] are connected to the same electric power source in accordance with a digital signal. It is assumed that they are connected to the electric power source A here. An equivalent circuit diagram of the conventional DAC immediately prior to the end of the reset period is shown in FIG.
12
A. Note that reference symbol C
A
denotes the combined capacitance of all the capacitors.
A write in period T
A
begins after the reset period T
R
is complete, and each bit of the digital signal, which has the arbitrary 0 or 1 information, controls the switches SW[
1
] to SW[n]. Electric charges are then supplied to the n capacitors by each capacitor connecting to the electric power source A or the electric power source B in accordance with information in each bit. This then becomes a normal state. An equivalent circuit diagram for this point is shown in FIG.
12
B. Note that the reference symbol C
T
denotes the combined capacitance of all the capacitors connected to the electric power source A, and that the reference symbol C
B
denotes the combined capacitance of the capacitors connected to the electric power source B.
By repeating the reset period T
R
and the write in period T
A
stated above, it is possible to convert the digital signal in to an analog signal.
As stated above, the capacitance divided DAC is capable of high speed operation with a relatively smaller surface area compared to a resistance divided DAC, and thus it is considered preferable in making flat panel displays smaller. However, if the number of bits of the digital signal is increased in order to make the flat panel display higher definition, it becomes difficult to suppress the amount of surface area occupied on the substrate, even with capacitance divided DACs.
If each capacitor of a capacitance divided DAC is designed with reduced size in order to reduce the occupied surface area, then the capacitor surface area corresponding to the lowest bit and its capacitance value become smaller. A small shift in the capacitance value develops due to causes such as shifts in the position of masks used during formation of the capacitor, patterning, and unforeseen parasitic capacitance. Therefore, if the capacitors are designed smaller, the ratio of shift in the capacitance value of the capacitor corresponding to the lowest bit becomes large, and it becomes difficult to form a capacitance divided DAC having good linearity.
Further, if the number of corresponding digital signal bits is increased with a resistance divided DAC, then not only does it become difficult to reduce the surface area, but the output resistance also becomes high, and high speed operation becomes difficult.
SUMMARY OF THE INVENTION
In view of the above stated problems, an object of the present invention is to manufacture a DAC capable of having a limited surface area, even if the number of digital signal bits is increased in order to a flat panel display further smaller in size of and have high definition, and which also has good linearity at high speed operation.
The applicants of the present invention considered using a resistance divided DAC or a selector circuit as a substitute for capacitors corresponding to the lower bits, which affect the inconsistent linearity of a capacitance divided DAC.
With the present invention, for example, one capacitor corresponding to the lower m bits of an n-bit digital signals D
1
to D
n
(m<n), and n−m capacitors corresponding to the upper n−m bits, are formed in a DAC corresponding to the n-bit digital signal. The one capacitor corresponding to the lower m bits of the digital signal is hereafter referred to as a lower bit correspondence capacitor (C
L
), and the n−m capacitors corresponding to the upper n−m bits are hereafter referred to as upper bit correspondence capacitors (C
U
).
The capacitance value of the lower bit correspondence capacitor is denoted by C (where C is a constant), and the capacitance values of the n−m upper bit correspondence capacitors are denoted by, in order from the lowest of the upper bits, C
U
[
1
]=C, C
U
[
2
]=2C, C
U
[
3
]=2
2
C, . . . , C
U
[n−m−1]=2
n−m−2
C, and C
U
[n−m]=2
n−m−1
C.
The DAC of the present invention is connected to an electric power source A (electric potential V
A
) and to an electric power source B (electric potential V
B
) having different electric potentials. Electrical charging of the n−m upper bit correspondence capacitors by the two electric power sources is controlled by each bit of the upper n−m bits of the digital signal.
Further, the lower m bits of the digital signal are converted into analog in the resistance divided DAC, or selector circuit, corresponding to the lower m bits in the DAC of the present invention, and input to a lower bit output line as an analog signal co

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