Burst architecture for a flash memory

Details Burst architecture for a flash memory Burst architecture for a flash memory

2001-04-09

2003-09-16

Kim, Hong (Department: 2186)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060, C365S230090, C365S193000, C365S185010, C711S103000, C711S167000

Reexamination Certificate

active

06621761

ABSTRACT:

BACKGROUND
The present invention relates generally to semiconductor memory devices. More particularly, the present invention relates to a burst architecture for a flash memory.
Flash random access memory (RAM), more commonly known as flash memory, is a form of non-volatile storage that uses a memory cell design with a floating gate. High voltages are applied to the memory cell inputs to program or store charge on the floating gate or to erase or remove charge from the floating gate. Programming occurs by hot electron transfer to place charge on the floating gate while erasure makes use of Fowler-Nordheim tunneling in which electrons pierce a thin dielectric material, reducing the amount of electronic charge on the floating gate. Erasing a cell sets the logical value of the cell to “I” while programming the cell sets the logical value to “0”. Aside from programming or erasing operations, a flash memory operates similarly to a randomly accessible read only memory (ROM). Conventionally, a flash memory chip, including the flash memory storage cells and support logic/circuitry, is made by fabricating layers of semiconductor material and interconnect layers of polysilicon and first and second metal layers onto a substrate. It will be appreciated that there are numerous integrated circuit fabrication techniques, involving more or fewer layers, which are applicable herein.
Flash memories are asked to meet continually increasing standards of system performance. One area where opportunities lie to increase the performance of flash memory is the area of burst mode flash memory. It would be desirable to implement a high performance flash memory capable of improved burst mode operation.


REFERENCES:
patent: 5604884 (1997-02-01), Thome et al.
patent: 5781500 (1998-07-01), Oh
patent: 5838990 (1998-11-01), Park et al.
patent: 5867447 (1999-02-01), Koshikawa
patent: 5923615 (1999-07-01), Leach et al.
patent: 6104667 (2000-08-01), Akaogi
patent: 6108243 (2000-08-01), Suzuki et al.
patent: 6111787 (2000-08-01), Akaogi et al.
patent: 6147905 (2000-11-01), Seino
patent: 6172936 (2001-01-01), Kitazaki
patent: 6205084 (2001-03-01), Akaogi
patent: 6215722 (2001-04-01), Park
patent: 6216180 (2001-04-01), Kendall et al.
patent: 6222767 (2001-04-01), Kendall et al.
patent: 6285585 (2001-09-01), Kurihara et al.
patent: 6304510 (2001-10-01), Nobunaga et al.
patent: 6314049 (2001-11-01), Roohparvar
patent: 6385688 (2002-05-01), Mills et al.
patent: 0 821 363 (1998-01-01), None

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