Tuneable ferroelectric decoupling capacitor

Details Tuneable ferroelectric decoupling capacitor Tuneable ferroelectric decoupling capacitor

1999-11-01

2003-01-14

Dinkins, Anthony (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S306100, C361S306300, C361S321400, C361S313000, C257S295000, C257S296000

Reexamination Certificate

active

06507476

ABSTRACT:

BACKGROUND
High performance integrated circuit chips such as microprocessors require large values of bypass capacitance located closely adjacent to the chip. In some recent designs, such as the Digital Equipment Corporation Alpha 600 MHz microprocessor, it has been necessary to wirebond the bypass capacitor directly to the chip. In this particular example, the “bypass capacitor” is itself a specialized P channel FET chip with a large thin oxide region. Capacitor values are typically 10 nanofarads or more. Practical values of inductance range from a fraction of a nanohenry to a few nanohenrys. A simple calculation shows that such circuit combinations lead to resonant frequencies very close to the clock frequency of the microprocessor. The microprocessor clock itself contains many harmonics of the basic clock frequency. Specific repetitive operations of the microprocessor are capable of generating still other harmonics and subharmonics. Thus, it becomes nearly impossible to escape harmonics or subharmonics that can excite the resonant frequency of the bypass capacitor and its ancillary inductance. Adding resistance to the inductance to provide critical damping, destroys the efficacy of the bypass capacitor.
Accordingly, a voltage supply bypass capacitor is needed for high performance integrated circuit chips which can be designed to provide maximum losses at selected frequencies.
SUMMARY OF THE INVENTION
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for configuring a bypass capacitor for use in conjunction with an integrated circuit device. In an exemplary embodiment of the invention, the method includes selecting mechanical dimensions for the bypass capacitor, the mechanical dimensions causing the bypass capacitor to exhibit electrical losses at a clock frequency of the integrated circuit device. The bypass capacitor preferably includes a ferroelectric dielectric material. In addition, the selection of mechanical dimensions for the bypass capacitor determines a mechanical resonance frequency for the bypass capacitor, with the mechanical resonance frequency corresponding to the clock frequency.
In a preferred embodiment, the selection of mechanical dimensions for the bypass capacitor additionally causes the bypass capacitor to exhibit electrical losses at least one multiple or submultiple of the clock frequency. The mechanical damping properties of the ferroelectric dielectric material are increased by the ferroelectric dielectric material comprising a perovskite-type oxide selected from a titanate system material such as barium titanate, strontium titanate, barium strontium titanate, lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate and barium lanthanum titanate; a niobate or tantalate system material such as lead magnesium niobate, lithium niobate lithium tantalate, potassium niobate and potassium tantalum niobate; a tungsten-bronze system material such as barium strontium niobate, lead barium niobate and barium titanium niobate; or a bi-layered perovskite system material such as strontium bismuth tantalate and bismuth titanate.


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patent: 5818079 (1998-10-01), Noma et al.
patent: 5969935 (1999-10-01), Kammerdiner et al.

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