Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-02-23
2003-03-11
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S534000
Reexamination Certificate
active
06531912
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit improved in parasitic capacitance of a voltage-dividing resistance in a high voltage generating circuit for a memory device.
It has been required for development of a non-volatile semiconductor memory to realize a highly accurate control to a high output voltage level for a device withstand voltage, and write and erasing operations.
FIG. 1
is a circuit diagram illustrative of a first conventional high voltage generating circuit for generating a highly accurate high voltage for writing and erasing operations of the non-volatile semiconductor memory. The first conventional high voltage generating circuit comprises a booster circuit
1
, a comparator
2
, and first and second voltage dividing resistances R
1
and R
2
. The booster circuit
1
has a first input terminal for receiving a clock signal CLK and a second input terminal connected to an output terminal of the comparator
2
for receiving a control signal Vc from the comparator
2
. The booster circuit
1
generates a high voltage output Vo which is outputted from its output terminal. A voltage dividing circuit is provided which comprises a series connection of the first and second voltage-dividing resistances R
1
and R
2
between the output terminal of the booster circuit
1
and a ground level. The first voltage-dividing resistance R
1
is connected in series between the output terminal of the booster circuit
1
and the second voltage-dividing resistance R
2
. The second voltage-dividing resistance R
2
is connected in series between the ground terminal and the first voltage-dividing resistance R
1
. The comparator
2
has a first input terminal connected to an output terminal of the voltage-dividing circuit or an intermediate point between the first and second voltage dividing resistances R
1
and R
2
for receiving a voltage Vi divided by the voltage-dividing circuit. The comparator
2
also has a second input terminal for receiving a reference voltage Vr for allowing the voltage Vi to be compared with the reference voltage Vr, whereby the comparator
2
generates the control signal Vc and output the same from its output terminal. The first voltage dividing resistance R
1
has a first parasitic capacitance C
2
. The second voltage dividing resistance R
2
has a second parasitic capacitance C
3
. Since the booster circuit
1
has a low capability of supplying the current, it is required to reduce the currents flowing through the series connections of the first and second voltage-dividing resistances R
1
and R
2
, The resistance values of the first and second voltage-dividing resistances R
1
and R
2
are required to be high, provided that the high relative accuracy in resistance value of each of the first and second voltage-dividing resistances R
1
and R
2
is also necessary. For those purposes, the first and second voltage-dividing resistances R
1
and R
2
may further comprise polysilicon resistances which are low in bias-dependency and are suitable to be higher resistances than the diffusion resistances.
The first and second voltage-dividing resistances R
1
and R
2
need larger occupying areas than other resistances, whereby the larger occupying areas of the first and second voltage-dividing resistances R
1
and R
2
result in the increases in parasitic capacitances C
2
and C
3
. The first voltage-dividing resistance R
1
has a first time constant which is defined by the resistance value and the parasitic capacitance value thereof. The second voltage-dividing resistance R
2
has a second time constant which is defined by the resistance value and the parasitic capacitance value thereof. The accuracy in the voltage level of the high voltage output depends on the time constant. As the time constants of the first and second voltage-dividing resistances R
1
and R
2
are increased, then the accuracy in the voltage level of the high voltage output is deteriorated.
FIG. 2
is a diagram illustrative of the waveform of the high voltage output of the first conventional high voltage generating circuit of FIG.
1
.
FIG. 2
shows a ripple width “v” represented by a vertical arrow mark, an expected level represented by a horizontal broken line, delay times of the comparator represented by two horizontal short arrow marks and a delay of the voltage-dividing resistance represented by a horizontal long arrow mark. The first time constant defined by the first voltage-dividing resistance R
1
and the first parasitic capacitance C
2
and the second time constant defined by the second voltage-dividing resistance R
2
and the second parasitic capacitance C
3
cause a delay in time of the divided voltage Vi appearing on the output terminal between the first and second voltage-dividing resistances R
1
and R
2
of the voltage-dividing circuit. The delay in time of the divided voltage Vi increases a delay time of a feed-back path from the output terminal of the booster circuit
1
to the output terminal of the comparator
2
. During this delay time period, it is difficult to control the booster circuit, whereby the high voltage output has a large ripple width and a deteriorated accuracy in its voltage level.
The ripple width is given by the following equation.
V={Dt
1
×(
R
1
×
C
2
)+
Dt
2
}×
Vdt
(1)
where “Dt
1
” is the delay of the voltage-dividing resistances, and “Dt
2
” is the delay of the comparator, and “Vdt” is a voltage rising rate per a unit time or a boosting capability.
FIG. 3
is a diagram illustrative of a result of the simulation to the first conventional circuit of FIG.
1
. The ripple width of the high voltage output is 700 mV. The large ripple width means the low accuracy in voltage level of the high voltage output. It is necessary for improving the accuracy in voltage level of the high voltage output to reduce the ripple width of the high voltage output- A second conventional high voltage generating circuit has been proposed for reducing the ripple width.
FIG. 4
is a circuit diagram illustrative of a second conventional high voltage generating circuit for generating a highly accurate high voltage for writing and erasing operations of the non-volatile semiconductor memory. The second conventional high voltage generating circuit further has a speed up capacitor C
1
. Namely, the second conventional high voltage generating circuit comprises a booster circuit
1
, a comparator
2
, and first and second voltage dividing resistances R
1
and R
2
as well as a capacitor C
1
so called to as speed up capacitor. The booster circuit
1
has a first input terminal for receiving a clock signal CLK and a second input terminal connected to an output terminal of the comparator
2
for receiving a control signal Vc from the comparator
2
. The booster circuit
1
generates a high voltage output Vo which is outputted from its output terminal. A voltage dividing circuit is provided which comprises a series connection of the first and second voltage-dividing resistances R
1
and R
2
between the output terminal of the booster circuit I and a ground level. The first voltage-dividing resistance R
1
is connected in series between the output terminal of the booster circuit
1
and the second voltage-dividing resistance R
2
. The second voltage-dividing resistance R
2
is connected in series between the ground terminal and the first voltage-dividing resistance R
1
. The comparator
2
has a first input terminal connected to an output terminal of the voltage-dividing circuit or an intermediate point between the first and second voltage dividing resistances R
1
and R
2
for receiving a voltage Vi divided by the voltage-dividing circuit, The comparator
2
also has a second input terminal for receiving a reference voltage Vr for allowing the voltage Vi to be compared with the reference voltage Vr, whereby the comparator
2
generates the control signal Vc and output the same from its output terminal. The first voltage dividing res
Cunningham Terry D.
Young & Thompson
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