Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-03-23
2003-04-15
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S189011, C365S189040
Reexamination Certificate
active
06549482
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of memories and more particularly to a technique to provide real-time access to flash memory features by use of a memory mapped input/output plane.
2. Description of the Related Art
A flash memory is a non-volatile electrically erasable and electrically programmable read-only semiconductor memory. Once programmed, the flash memory retains the program data until the memory is erased. In a typical flash memory structure, several blocks of flash memory are configured together on a flash memory device. A variety of flash memory devices are known in the art, but generally, a flash memory device is comprised of a plurality of memory cells, in which each cell includes a metal oxide semiconductor (MOS) transistor. Each flash transistor cell includes an isolated or floating gate that is programmed typically by electron injection from the channel.
In one typical configuration, a flash memory is partitioned into a plurality of memory blocks and in which operations are performed on a selected block or blocks. For example, a block erase routine is performed on each given block to erase the memory cells of that block. In general practice, flash memory devices are electrically erased to reset the state of the cells of a given block. Subsequently, over-erased cells are repaired and all cells verified to ensure that the cells are not in an over-erased condition. Once this procedure has been performed the cells can then be programmed.
In a typical flash operation, the memory cells of a flash array (or block) are read to determine if a selected cell is either in a programmed or a non-programmed state. Generally, the programmed cells require a higher threshold voltage to activate so that with a properly selected voltage on the control grid of a flash cell, the cell will conduct or not conduct depending on the programmed
on-programmed state of the particular cell.
Because of the nonvolatile nature of flash memories, these memory devices are utilized in a number of products. For example, cellular phones utilize flash memory cells to store various programmed information which can be retained even when the phone is turned off. The programmed information will generally include program code for execution by a processor or a controller. In a typical initialization procedure, the processor or controller coupled to operate with the flash memory will generally access the flash memory to initiate a boot sequence. The boot sequence is then followed by an applications program, which is stored in the flash memory. One program will configure the flash memory according to various information/parameters associated with the flash device. Some or all of these parameters are written to particular locations in the flash to provide the flash configuration.
However, since prior art flash memory devices typically require specialized commands to perform a flash operation, these devices cannot read data from the flash array and write to the array at the same time. That is, when a flash is in the flash read mode reading code from the flash memory, it cannot write data to memory. Alternatively, when the flash device is in one of the other modes (such as a write mode), the flash cannot read from the flash array. Once the executable command is completed (or suspended in some instances), a read flash array command is written to the flash device to return the flash to the flash read mode. Accordingly, existing flash devices can either read from the flash memory array or perform some other executable operation (other than flash read) on memory, but the device cannot do both operations at the same time.
When the processor is executing code from flash in the read mode, the flash memory device needs to be switched to another mode first (typically by writing the corresponding command to the flash device), before other functions can be performed, such as writing to the flash memory. Thereafter, in order to read the stored data (such as the program code mentioned above), the flash device needs to be placed back into the flash read mode (by writing a flash read command to the flash device). In order to be able to execute the code from flash while having access to the flash memory to perform other functions, one prior art technique loads the flash data elsewhere, so that the code can be executed while other data locations can be accessed. Otherwise, constant switching between flash read and other modes is required to read data (for example, the flash code) normally present in the data array/blocks of the flash memory device.
For example, in order to configure the flash device, the processor executes the flash code to configure the device. Configuration parameters are mapped to designated locations in the flash memory. This procedure is sometimes referred to as mapping the configuration plane and is done during initialization of the flash device (such as at power on reset). One existing practice is to transfer the contents of the flash memory (including the code for configuring the flash device) to another storage device such as RAM (random access memory), so that the code can be executed from RAM. This way the flash code, which is now in RAM, can be read and executed by the processor while executable commands can operate on the flash device. This way, an executable command instruction to the flash device can be performed, while reading the code from RAM.
This is typically the routine followed when a flash device is initialized (such as at power on reset), in which the processor, after loading flash data to RAM, executes the code from RAM to access the flash memory to configure the flash device as part of the initialization. Accordingly, in one prior art technique, the data from the flash memory device is transferred to RAM to map the configuration plane, so that the flash device need not be repeatedly written to switch modes between flash read and other executable modes.
It is to be noted that performance would be improved significantly if a mechanism was present to allow a flash device to execute other command instructions while reading flash data from memory, without transferring the flash data to another memory device.
REFERENCES:
patent: 5546561 (1996-08-01), Kynett et al.
patent: 6031757 (2000-02-01), Chuang et al.
patent: 6307779 (2001-10-01), Roohparvar
Intel Corporation, “3 Volt Advanced+ Boot Block Flash Memory”; Oct., 2000; pp 1-63.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Le Thong
Nelms David
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